ISL6625A
8
FN7978.0
September 19, 2012
Application Information
Layout Considerations
During switching of the devices, the parasitic inductances of the
PCB and the power devices’ packaging (both upper and lower
MOSFETs) leads to ringing, possibly in excess of the absolute
maximum rating of the devices. Careful layout can help minimize
such unwanted stress. The following advice is meant to lead to
an optimized layout:
• Keep decoupling loops (VCC-GND and BOOT-PHASE) as short
as possible.
• Minimize trace inductance, especially low-impedance lines: all
power traces (UGATE, PHASE, LGATE, GND) should be short
and wide, as much as possible.
• Minimize the inductance of the PHASE node: ideally, the
source of the upper and the drain of the lower MOSFET should
be as close as thermally allowable.
• Minimize the input current loop: connect the source of the
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source of
lower MOSFETs as possible.
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the IC
and/or connected to buried power ground plane(s) with thermal
vias. This combination of vias for vertical heat escape, extended
surface copper islands, and buried planes combine to allow the
IC and the power switches to achieve their full thermal potential.
Upper MOSFET Self Turn-On Effect at
Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high dV/dt
rate while the driver outputs are floating, due to self-coupling via
the internal C
GD
of the MOSFET, the gate of the upper MOSFET
could momentarily rise up to a level greater than the threshold
voltage of the device, potentially turning on the upper switch.
Therefore, if such a situation could conceivably be encountered,
it is a common practice to place a resistor (R
UGPH
) across the
gate and source of the upper MOSFET to suppress the Miller
coupling effect. The value of the resistor depends mainly on the
input voltage’s rate of rise, the C
GD
/C
GS
ratio, as well as the
gate-source threshold of the upper MOSFET. A higher dV/dt, a
lower C
DS
/C
GS
ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of the
internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components such as lead
inductances and PCB capacitances are also not taken into
account. Figure 6 provides a visual reference for this
phenomenon and its potential solution.
V
GS_MILLER
dV
dt
-------
RC
rss
1e
V–
DS
dV
dt
-------
RC⋅
iss
⋅
----------------------------------
–
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎜⎟
⎛⎞
⋅⋅=
RR
UGPH
R
GI
+=
C
rss
C
GD
=
C
iss
C
GD
C
GS
+=
(EQ. 5)
FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE UPPER
MOSFET MILLER COUPLING
VIN
Q
UPPER
D
S
G
R
G
R
UGPH
BOOT
C
DS
C
GS
C
GD
PHASE
VCC
ISL6625A
C
BOOT
UGATE
>
10kΩ
