ISL6625A
6
FN7978.0
September 19, 2012
Description
Operation and Adaptive Shoot-through
Protection
Designed for high speed switching, the ISL6625A MOSFET driver
controls both high-side and low-side N-Channel FETs from one
externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 2). After a short propagation delay [t
PDLL
], the
lower gate begins to fall. Typical fall time [t
FL
] is provided in the
“Electrical Specifications” on page 3. Following a 25ns blanking
period, adaptive shoot-through circuitry monitors the LGATE
voltage and turns on the upper gate following a short delay time
[t
PDHU
] after the LGATE voltage drops below ~1.75V. The upper
gate drive then begins to rise [t
RU
] and the upper MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short propagation
delay [t
PDLU
] is encountered before the upper gate begins to fall
[t
FU
]. The adaptive shoot-through circuitry monitors the
UGATE-PHASE voltage and turns on the lower MOSFET a short
delay time [t
PDHL
] after the upper MOSFET’s PHASE voltage drops
below +0.8V or 40ns after the upper MOSFET’s gate voltage
[UGATE-PHASE] drops below ~1.75V. The lower gate then rises
[t
RL
], turning on the lower MOSFET. These methods prevent both
the lower and upper MOSFETs from conducting simultaneously
(shoot-through), while adapting the dead time to the gate charge
characteristics of the MOSFETs being used.
This driver is optimized for voltage regulators with large step down
ratio. The lower MOSFET is usually sized larger compared to the
upper MOSFET because the lower MOSFET conducts for a longer
time during a switching period. The lower gate driver is therefore
sized much larger to meet this application requirement. The 0.8Ω
ON-resistance and 3A sink current capability enable the lower gate
driver to absorb the current injected into the lower gate through
the drain-to-gate capacitor of the lower MOSFET and help prevent
shoot-through caused by the self turn-on of the lower MOSFET due
to high dV/dt of the switching node.
Three-State PWM Input
A unique feature of ISL6625A and other Intersil drivers is the
addition of a three-state shutdown window to the PWM input. If
the PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and both
MOSFET gates are pulled and held low. The shutdown state is
removed when the PWM signal moves outside the shutdown
window. Otherwise, the PWM rising and falling thresholds
outlined in the “Electrical Specifications” on page 3 determine
when the lower and upper gates are enabled. This feature helps
prevent a negative transient on the output voltage when the
output is shut down, eliminating the Schottky diode that is used
in some systems for protecting the load from reversed output
voltage events.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored. Once the
rising VCC voltage exceeds rising POR threshold, operation of the
driver is enabled and the PWM input signal takes control of the
gate drives. If VCC drops below the POR falling threshold,
operation of the driver is disabled.
Pre-POR Overvoltage Protection
While VCC is below its POR level, the upper gate is held low and
LGATE is connected to the PHASE pin via an internal 30kΩ
(typically) resistor. By connecting the PHASE node to the gate of
the low side MOSFET, the driver offers some passive protection to
the load if the upper MOSFET(s) is or becomes shorted. If the
PHASE node goes higher than the gate threshold of the lower
MOSFET, it results in the progressive turn-on of the device and
the effective clamping of the PHASE node’s rise. The actual
PHASE node clamping level depends on the lower MOSFET’s
electrical characteristics, as well as the characteristics of the
input supply and the path connecting it to the respective PHASE
node.
Internal Bootstrap Device
The ISL6625A features an internal bootstrap Schottky diode
equivalent circuit implemented by swichers with typical on
resistance of 40Ω and no typical diode forward voltage drop.
Simply adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. The bootstrap function is
also designed to prevent the bootstrap capacitor from
overcharging due to the large negative swing at the trailing-edge
of the PHASE node. This reduces the voltage stress on the BOOT
to PHASE pins.
The bootstrap capacitor must have a maximum voltage rating
well above the maximum voltage intended for UVCC. Its
minimum capacitance value can be estimated from Equation 1:
Where Q
G1
is the amount of gate charge per upper MOSFET at
V
GS1
gate-source voltage and N
Q1
is the number of control
MOSFETs. The ΔV
BOOT_CAP
term is defined as the allowable
droop in the rail of the upper gate drive. Select results are
exemplified in Figure 4.
C
BOOT_CAP
Q
UGATE
ΔV
BOOT_CAP
--------------------------------------
≥
Q
UGATE
Q
G1
UVCC•
V
GS1
------------------------------------
N
Q1
•=
(EQ. 1)
