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NCP1800DM42R2G
P1-P3
P4-P6
P7-P9
P10-P12
P13-P14
NCP1800
http://onsemi.com
7
End of Charge
CFLG:Low
OUT
:High
Full−Charge
CFLG:High
OUT
:1 I
REG
Fault Detected OR V
CDIS
= Low
No Fault Detected
I
SNS
> 0.1 I
REG
V
SNS
< V
REG
Pre−Charge
CFLG:High
OUT
:0.1 I
REG
T
rickle Charge
CFLG:Low
OUT
:V
REG
Final Charge
CFLG:High
OUT
:V
REG
V
SNS
< V
PCTH
Fault Modes:
1. Charger Low Output (V
CC
< V
UVLO
)
2. Runaway Charger (V
CC
> V
OVLO
)
3. Battery Removed (V
SNS
> V
SOVLO
)
Figure 14. NCP1800 State Machine Diagram
V
SNS
≥
V
PCTH
V
SNS
≥
V
REG
I
SNS
≤
0.1 I
REG
Fault
Detected OR
V
CDIS
= Low
Fault Detected
OR
V
CDIS
= Low
Fault Detected
OR
V
CDIS
= Low
V
UVLO
< V
CC
< V
OVLO
& V
SNS
< V
SOVLO
NCP1800
http://onsemi.com
8
Conditioning Phase
Start
V
oltage Regulation Phase
Set CFLG Low
Set I
CHARGE
= I
REG
/10
Set CFLG HIGH
Fault Mode
OR
V
CDIS
= LOW
N
Y
V
SNS
< V
PCTH
Fault Mode
OR
V
CDIS
= LOW
I
SNS
< I
REG
/10
N
Figure 15. NCP1800 Charging Operational Flow Chart
Set CFLG LOW
Y
Fault Mode
OR
V
CDIS
= LOW
N
Y
Set I
CHARGE
= I
REG
N
N
Y
Current Regulation Phase
Fault Mode
OR
V
CDIS
= LOW
V
SNS
> V
REG
N
N
Y
Y
Fault Mode
OR
V
CDIS
= LOW
N
Y
Y
Fault Modes:
1. Charger Low Output (V
CC
< V
UVLO
)
2. Runaway Charger (V
CC
> V
OVLO
)
3. Battery Removed (V
SNS
> V
SOVLO
)
NCP1800
http://onsemi.com
9
V
REG
V
PCTH
I
REG
0.1 x I
REG
CFLG = Low
(I
SNS
< 0.1 X I
REG
)
Pre−Charge
Phase
Full−Charge
Phase
Final Charge
Phase
T
rickle Charge
Phase
V
oltage
Current
time
time
Figure 16. T
ypical Charging Algorithm
CFLG = High
0.9 V
Charge Status
Conditions
CFLG Pin
Pre−Charge, Full−Charge and Final Charge
High−Z
End−of−Charge, T
rickle Charge and Faults
Low
P1-P3
P4-P6
P7-P9
P10-P12
P13-P14
NCP1800DM42R2G
Mfr. #:
Buy NCP1800DM42R2G
Manufacturer:
ON Semiconductor
Description:
IC CTRLR BATT CHRGR CC/CV 8MICRO
Lifecycle:
New from this manufacturer.
Delivery:
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