1. General description
The 74LVU04 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HCU04.
The 74LVU04 is a general purpose hex inverter. Each of the six inverters is a single stage
with unbuffered outputs.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Applications
Linear amplifier
Crystal oscillator
Astable multivibrator
74LVU04
Hex unbuffered inverter
Rev. 7 — 18 September 2014 Product data sheet
74LVU04 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 18 September 2014 2 of 20
NXP Semiconductors
74LVU04
Hex unbuffered inverter
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVU04N 40 Cto+125C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LVU04D 40 Cto+125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVU04DB 40 Cto+125C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LVU04PW 40 Cto+125C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVU04BQ 40 Cto+125C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Circuit diagram (one
inverter)
PQD
$
<
$
<
$
<
$
<
$
<
 
$
<


PQD




001aah110
100 Ω
V
CC
nA nY
V
CC
V
CC
170 Ω
74LVU04 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 18 September 2014 3 of 20
NXP Semiconductors
74LVU04
Hex unbuffered inverter
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
74LVU04
1A V
CC
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND 4Y
001aah108
1
2
3
4
5
6
7
8
10
9
12
11
14
13
001aah109
74LVU04
Transparent top view
3Y 4A
3A
V
CC
(1)
5Y
2Y 5A
2A 6Y
1Y 6A
GND
4Y
1A
V
CC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1A 1 data input
1Y 2 data output
2A 3 data input
2Y 4 data output
3A 5 data input
3Y 6 data output
GND 7 ground (0 V)
4Y 8 data output
4A 9 data input
5Y 10 data output
5A 11 data input
6Y 12 data output
6A 13 data input
V
CC
14 supply voltage

74LVU04PW,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Inverters HEX INVERTER (UNBUF)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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