12
FN9044.2
August 9, 2006
Out-of-Phase Operation
The two PWM controllers in the ISL6443 operate 180
o
out-of-
phase to reduce input ripple current. This reduces the input
capacitor ripple current requirements, reduces power supply-
induced noise, and improves EMI. This effectively helps to
lower component cost, save board space and reduce EMI.
Dual PWMs typically operate in-phase and turn on both upper
FETs at the same time. The input capacitor must then support
the instantaneous current requirements of both controllers
simultaneously, resulting in increased ripple voltage and
current. The higher RMS ripple current lowers the efficiency
due to the power loss associated with the ESR of the input
capacitor. This typically requires more low-ESR capacitors in
parallel to minimize the input voltage ripple and ESR-related
losses, or to meet the required ripple current rating.
With dual synchronized out-of-phase operation, the high-side
MOSFETs of the ISL6443 turn on 180
o
out-of-phase. The
instantaneous input current peaks of both regulators no longer
overlap, resulting in reduced RMS ripple current and input
voltage ripple. This reduces the required input capacitor ripple
current rating, allowing fewer or less expensive capacitors, and
reducing the shielding requirements for EMI. The typical
operating curves show the synchronized 180° out-of-phase
operation.
Input Voltage Range
The ISL6443 is designed to operate from input supplies
ranging from 4.5V to 24V. However, the input voltage range
can be effectively limited by the available maximum duty
cycle (D
MAX
= 93%).
where,
Vd1 = Sum of the parasitic voltage drops in the inductor
discharge path, including the lower FET, inductor and PC
board.
Vd2 = Sum of the voltage drops in the charging path,
including the upper FET, inductor and PC board resistances.
The maximum input voltage and minimum output voltage is
limited by the minimum on-time (t
ON(min)
).
where, t
ON(min)
= 30ns
Gate Control Logic
The gate control logic translates generated PWM signals into
gate drive signals providing amplification, level shifting and
shoot-through protection. The gate drivers have some circuitry
that helps optimize the ICs performance over a wide range of
operational conditions. As MOSFET switching times can vary
dramatically from type to type and with input voltage, the gate
control logic provides adaptive dead time by monitoring real
gate waveforms of both the upper and the lower MOSFETs.
Shoot-through control logic provides a 20ns deadtime to ensure
that both the upper and lower MOSFETs will not turn on
simultaneously and cause a shoot-through condition.
Gate Drivers
The low-side gate driver is supplied from VCC_5V and
provides a peak sink/source current of 400mA. The high-side
gate driver is also capable of 400mA current. Gate-drive
voltages for the upper N-Channel MOSFET are generated by
the flying capacitor boot circuit. A boot capacitor connected
from the BOOT pin to the PHASE node provides power to the
high side MOSFET driver. To limit the peak current in the IC,
an external resistor may be placed between the UGATE pin
and the gate of the external MOSFET. This small series
resistor also damps any oscillations caused by the resonant
tank of the parasitic inductances in the traces of the board an
the FET’s input capacitance.
At start-up the low-side MOSFET turns on and forces
PHASE to ground in order to charge the BOOT capacitor to
5V. After the low-side MOSFET turns off, the high-side
MOSFET is turned on by closing an internal switch between
BOOT and UGATE. This provides the necessary gate-to-
source voltage to turn on the upper MOSFET, an action that
boosts the 5V gate drive signal above VIN. The current
required to drive the upper MOSFET is drawn from the
internal 5V regulator.
Protection Circuits
The converter output is monitored and protected against
overload, short circuit and undervoltage conditions. A
sustained overload on the output sets the PGOOD low and
initiates hiccup mode.
Overcurrent Protection
Both PWM controllers use the lower MOSFET’s on-
resistance, r
DS(ON)
, to monitor the current in the converter.
The sensed voltage drop is compared with a threshold set by
a resistor connected from the OCSETx pin to ground.
V
IN min()
V
OUT
V
d1
+
0.93
--------------------------------
⎝⎠
⎛⎞
V
d2
V
d1
–+=
V
IN max()
V
OUT
t
ON min()
300kHz×
--------------------------------------------------- -
≤
BOOT
UGATE
PHASE
VCC_5V
VIN
ISL6443
FIGURE 15.
R
OCSET
7()R
CS
()
I
OC
()R
DS on()
()
-------------------------------------------
=
ISL6443
