Rev B 11/16/15 10 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
2.5V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
3.3V LVCMOS Output Load AC Test Circuit
2.5V LVCMOS Output Load AC Test Circuit
LVCMOS Output Duty Cycle/Pulse Width/Period
SCOPE
Qx
nQx
V
EE
V
CC,
2V
-1.3V± 0.165V
V
CCA,
V
CCO_LVPECL
V
CC,
V
CCA,
V
CCO_LVPECL
2V
-0.5V±0.125V
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
SCOPE
Qx
GND
1.65V±5%
-1.65V±5%
V
CCA,
V
CC,
V
CCO_LVCMOS
SCOPE
Qx
GND
V
CC,
V
CCA,
V
CCO_LVCMOS
1.25V±5%
-1.25V±5%
REF_OUT
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
V
CCO_CMOS
2
t
PW
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
11 Rev B 11/16/15
843001I-22 DATA SHEET
Parameter Measurement Information, continued
LVPECL Output Duty Cycle/Pulse Width/Period
LVPECL Output Rise/Fall Time
LVCMOS Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 843001I-22 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
CC,
V
CCA,
V
CCO_X
should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
CC
pin and also shows that V
CCA
requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the V
CCA
pin.
Figure 1. Power Supply Filtering
Q
nQ
Q
nQ
20%
80%
80%
20%
t
R
t
F
REF_OUT
V
CC
V
CCA
3.3V or 2.5V
10Ω
10µF.01µF
.01µF
Rev B 11/16/15 12 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843001I-22 DATA SHEET
Crystal Input Interface
The 843001I-22 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 26.5625MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and R2
can be 100. This can also be accomplished by removing R1 and
making R2 50. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22pF
C2
22pF
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50
Ω
0.1µf
R1
R2
V
DD
V
DD

843001AGI-22LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 1 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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