CY62137VNLL-70ZSXA

CY62137VN MoBL
®
Document #: 001-06497 Rev. *A Page 4 of 11
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT V
TH
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
CC
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R1
R2
(a)
Rise Time:
1 V/ns
Fall Time:
1 V/ns
(c)
Parameters Value Unit
R1 1105 Ohms
R2 1550 Ohms
R
TH
645 Ohms
V
TH
1.75 Volts
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
[3]
Max. Unit
V
DR
V
CC
for Data Retention 1.0 V
I
CCDR
Data Retention Current V
CC
= 1.0V, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V;
No input may exceed V
CC
+ 0.3V
Ind’l/Auto-A 0.5 7.5 µA
Auto-E 10
t
CDR
[5]
Chip Deselect to Data
Retention Time
0ns
t
R
Operation Recovery Time t
RC
ns
Data Retention Waveform
V
CC
(min.)V
CC
(min.)
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
t
R
CE
V
CC
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CY62137VN MoBL
®
Document #: 001-06497 Rev. *A Page 5 of 11
Switching Characteristics Over the Operating Range
[6]
Parameter Description
55 ns 70 ns
UnitMin. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 55 70 ns
t
AA
Address to Data Valid 55 70 ns
t
OHA
Data Hold from Address Change 10 10 ns
t
ACE
CE LOW to Data Valid 55 70 ns
t
DOE
OE LOW to Data Valid 25 35 ns
t
LZOE
OE LOW to Low-Z
[7]
55ns
t
HZOE
OE HIGH to High-Z
[7, 8]
25 25 ns
t
LZCE
CE LOW to Low-Z
[7]
10 10 ns
t
HZCE
CE HIGH to High-Z
[7, 8]
25 25 ns
t
PU
CE LOW to Power-up 0 0 ns
t
PD
CE HIGH to Power-down 55 70 ns
t
DBE
BHE / BLE LOW to Data Valid 55 70 ns
t
LZBE
(9)
BHE / BLE LOW to Low-Z 5 5 ns
t
HZBE
BHE / BLE HIGH to High-Z 25 25 ns
Write Cycle
[10, 11]
t
WC
Write Cycle Time 55 70 ns
t
SCE
CE LOW to Write End 45 60 ns
t
AW
Address Set-up to Write End 45 60 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-up to Write Start 0 0 ns
t
PWE
WE Pulse Width 40 50 ns
t
SD
Data Set-up to Write End 25 30 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High-Z
[7, 8]
20 25 ns
t
LZWE
WE HIGH to Low-Z
[7]
510ns
t
BW
BHE / BLE LOW to End of Write 50 60 ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to V
CC
typ., and output loading of the specified
I
OL
/I
OH
and 30 pF load capacitance.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. If both byte enables are toggled together this value is 10 ns.
10.The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
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CY62137VN MoBL
®
Document #: 001-06497 Rev. *A Page 6 of 11
Switching Waveforms
Read Cycle No. 1
[12, 13]
Read Cycle No. 2
[13, 14]
Notes:
12.Device is continuously selected. OE
, CE = V
IL
.
13.WE
is HIGH for read cycle.
14.Address valid prior to or coincident with CE
transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
RC
t
ACE
t
DBE
t
LZBE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE
t
DOE
t
LZOE
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CY62137VNLL-70ZSXA

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 2M PARALLEL 44TSOP II
Lifecycle:
New from this manufacturer.
Delivery:
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