P5020/P5010 Features List
Two (P5020) or one (P5010)
single threaded e5500 cores
built on Power Architecture
®
technology
• Up to 2.0 GHz with 64-bit ISA support (Power Architecture V2.06 compliant)
• Three levels of instruction: User, supervisor, hypervisor
• Hybrid 32-bit mode to support legacy software and transition to 64-bit
architecture
CoreNet platform cache (CPC) • 2.0 MB configured as dual 1 MB blocks (1 MB only for P5010)
Hierarchical interconnect fabric • CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet endpoints
• QMAN fabric supporting packet-level queue management and quality of
service scheduling
Two 64-bit DDR3/3L SDRAM
memory controllers with ECC
and interleaving support
• Up to 1333 MT/s
• Memory pre-fetch engine
DPAA incorporating acceleration
for the following functions
• Packet parsing, classification and distribution (FMAN)
• QMAN for scheduling, packet sequencing and congestion management
• Hardware BMAN for buffer allocation and de-allocation
• Cryptography acceleration (SEC 4.2) at up to 40 Gb/s
• RegEx pattern matching acceleration (PME 2.1) at up to 10 Gb/s
SerDes • 18 lanes at up to 5 Gb/s
• Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA
Ethernet interfaces • One 10 Gb/s Ethernet MACs
• 5x 1 Gb/s Ethernet MACs
High-speed peripheral interfaces • Four PCI Express 2.0 controllers
• Two Serial RapidIO
®
controllers/ports (sRIO port) v1.3-compliant with
features of v2.1
• Two serial ATA (SATA 2.0) controllers
Additional peripheral interfaces • Two Full-Speed USB 2.0 controllers with integrated PHY
• Enhanced secure digital host controller (SD/MMC/eMMC)
• Enhanced serial peripheral interface
• Four I
2
C controllers
• Four UARTs
• Integrated flash controller supporting NAND and NOR flash
DMA • Dual four channel
Support for hardware
virtualization and partitioning
enforcement
• Extra privileged level for hypervisor support
QorIQ trust architecture 1.1 • Secure boot, secure debug, tamper detection, volatile key storage
DPAA Hardware Accelerators
Frame manager (FMAN) 12 Gb/s classify, parse
and distribute
Buffer manager (BMAN) 64 buffer pools
Queue manager (QMAN) Up to 2
24
queues
Security (SEC) 17 Gb/s: 3 DES, AES
Pattern matching engine
(PME)
10 Gb/s aggregate
RapidIO
®
manager Supports type 9 and
type 11 messaging
RAID5/6 engine Calculates parity for
network attached
storage and direct
attached storage
applications
Data Path Acceleration Architecture
(DPAA)
The P5020 integrates QorIQ DPAA, an
innovative multicore infrastructure for
scheduling work to cores (physical and virtual),
hardware accelerators and network interfaces.
The FMAN, a primary element of the DPAA,
parses headers from incoming packets and
classifies and selects data buffers with optional
policing and congestion management. The
FMAN passes its work to the QMAN, which
assigns it to cores or accelerators with a multi-
level scheduling hierarchy. The P5020 also
offers accelerators for cryptography, enhanced
regular expression pattern matching and
RAID5/6 offload.
System Peripherals and Networking
For networking, the FMAN supports one
10 Gb/s and 5x 1 Gb/s MAC controllers that
connect to PHYs, switches and backplanes
over RGMII, SGMII and XAUI. High-speed
system expansion is supported through four
PCI Express
®
v2.0 controllers that support a
variety of lane widths. Other peripherals include
SATA, SD/MMC, I
2
C, UART, SPI, NOR/NAND
controller, GPIO and dual 1333 MT/s DDR3/3L
controllers.
Software and Tool Support
• Enea: Real-time operating system support
and virtualization software
• Green Hills: Comprehensive portfolio of
software and hardware development tools,
trace tools, real-time operating systems
and virtualization software
• Mentor Graphics
®
: Commercial-grade
Linux solution
• QNX
®
: Real-time OS and development tool
support
• QorIQ P5020 development system
(P5020DS-PB)
For more information, please visit freescale.com/QorIQ
Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a
trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.
The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and
service marks licensed by Power.org. © 2012, 2013 Freescale Semiconductor,Inc.
Document Number: QP5020FS REV 4
