ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK EPROM VCXO AND SYNTHESIZER
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK 7
ICS270 REV F 051310
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15 pF load.
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency F
IN
Fundamental crystal 5 27 MHz
Output Frequency 0.314 200 MHz
Crystal Pullability F
P
0V< VIN < 3.3 V, Note 1 100 ppm
VCXO Gain VIN = VDD/2 +
1 V,
Note 1
110 ppm/V
Output Rise/Fall Time t
OF
80% to 20%, high drive,
Note 2
1.0 ns
Output Rise/Fall Time t
OF
80% to 20%, low drive,
Note 2
2.0 ns
Duty Cycle Note 3 40 49-51 60 %
Power-up time
PLL lock-time from
power-up
410ms
PDTS
goes high until
stable CLK output
0.6 2 ms
One Sigma Clock Period Jitter Configuration Dependent 50 ps
Maximum Absolute Jitter t
ja
Deviation from Mean,
Configuration Dependent
+200 ps
Pin-to-Pin Skew Low Skew Outputs -250 250 ps
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
JA
Still air 93 ° C/W
θ
JA
1 m/s air flow 78 ° C/W
θ
JA
3 m/s air flow 65 ° C/W
Thermal Resistance Junction to Case θ
JC
20 ° C/W
ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK EPROM VCXO AND SYNTHESIZER
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK 8
ICS270 REV F 051310
Marking Diagram
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temp. range (if applicable).
4. “L” denotes Pb (lead) free package.
5. Bottom marking: country of origin.
1
10
11
20
270PGL
######
YYWW
1
10
11
20
270PGIL
######
YYWW
ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK EPROM VCXO AND SYNTHESIZER
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK 9
ICS270 REV F 051310
Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
24
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
.10 (.004)
C
c
L
Millimeters Inches
Symbol Min Max Min Max
1.20 .047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.19 0.30 0.007 0.012
C 0.09 0.20 0.0035 0.008
D 6.40 6.60 0.252 0.260
E 6.40 BASIC 0.252 BASIC
E1 4.30 4.50 0.169 0.177
e 0.65 Basic 0.0256 Basic
L 0.450.75.018.030
α 0° 8° 0° 8°
20

270PGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner TRIPLE PLL VCXO CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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