www.fairchildsemi.com
REV. 1.08 12/21/00
Features
8-bit resolution
150 megapixels per second
0.2% linearity error
Sync and blank controls
1.0V p-p video into 37.5
or 75
load
Internal bandgap voltage reference
Double-buffered data for low distortion
TTL-compatible inputs
Low glitch energy
Single +5 Volt power supply
Applications
Video signal conversion
– RGB
YC
B
C
R
– Composite, Y, C
Multimedia systems
Image processing
True-color graphics systems
Description
FMS3810/3815 products are low-cost triple D/A converters
that are tailored to fit graphics and video applications where
speed is critical. Two speed grades are available:
TTL-level inputs are converted to analog current outputs that
can drive 25–37.5
loads corresponding to doubly-terminated
50–75
loads. A sync current following SYNC input timing
is added to the I
OG
output. BLANK will override RGB
inputs, setting I
OG
, I
OB
and I
OR
currents to zero when
BLANK = L. Although appropriate for many applications
the internal 1.235V reference voltage can be overridden by
the V
REF
input.
Few external components are required, just the current
reference resistor, current output load resistors, and
decoupling capacitors.
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
FMS3810 100 Ms/s
FMS3815 150 Ms/s
Block Diagram
8 bit D/A
Converter
SYNC
8
SYNC
CLOCK
G
7-0
COMP
+1.235V
Ref
IO
G
BLANK
8 bit D/A
Converter
8
B
7-0
IO
B
8 bit D/A
Converter
8
R
7-0
IO
R
R
REF
V
REF
FMS3810/3815
Triple Video D/A Converters
3 x 8 bit, 150 Ms/s
FMS3810/3815 PRODUCT SPECIFICATION
2
REV. 1.08 12/21/00
Functional Description
Within the FMS3810/3815 are three identical 10-bit D/A
converters, each with a current source output. External loads
are required to convert the current to voltage outputs. Data
inputs RGB
7-0
are overridden by the BLANK input. SYNC
= H activates, sync current from I
OS
for sync-on-green video
signals.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes t
DO
after the rising
edge of CLK.
SYNC
and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source that is
connected to the green D/A converter. SYNC = H adds a 40
IRE sync pulse to the green output, SYNC = L sets the green
output to 0.0 Volts during the sync tip. SYNC and BLANK
are registered on the rising edge of CLK.
Figure 1. Nominal Output Levels
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = H, the D/A inputs are added to a pedestal which
offsets the current output. If BLANK = L, data inputs and the
pedestal are disabled.
D/A Outputs
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor connected
between R
REF
and GND.
Normally, a source termination resistor of 75 Ohms is
connected between the D/A current output pin and GND
near the D/A converter. A 75 Ohm line may then be
connected with another 75 Ohm termination resistor at the
far end of the cable. This “double termination” presents the
D/A converter with a net resistive load of 37.5 Ohms.
The FMS3810/3815 may also be operated with a single 75
Ohm terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
R
REF
should be doubled.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference voltage
is +1.235 Volts with a 3K
source resistance. An external
voltage reference may be connected to the V
REF
pin,
overriding the internal voltage reference.
A 0.1µF capacitor must be connected between the COMP
pin and V
DD
to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be
connected to V
DD
pins with 0.1 and 0.01 µF decoupling
capacitors placed adjacent to each V
DD
pin or pin pair.
High slew-rate of digital data makes capacitive coupling to
the outputs of any D/A converter a potential problem. Since
the digital signals contain high-frequency components of the
CLK signal, as well as the video output signal, the resulting
data feedthrough often looks like harmonic distortion or
reduced signal-to-noise performance. All ground pins should
be connected to a common solid ground plane for best
performance.
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
PRODUCT SPECIFICATION FMS3810/3815
REV. 1.08 12/21/00
3
Table 1. Output Voltage versus Input Code, SYNC
and BLANK
V
REF
= 1.235 V, R
REF
= 590
, R
L
= 37.5
Pin Assignments
RGB7-0 (MSB…LSB)
Blue and Red Green
SYNC BLANK V
OUT
SYNC BLANK V
OUT
1111 1111 X 1 0.714 1 1 1.000
1111 1111 X 1 0.714 0 1 0.714
1111 1110 X 1 0.711 1 1 0.997
1111 1101 X 1 0.709 1 1 0.995
0000 0000 X 1 0.385 1 1 0.671
1111 1111 X 1 0.383 1 1 0.669
0000 0010 X 1 0.059 1 1 0.345
0000 0001 X 1 0.057 1 1 0.343
0000 0000 X 1 0.054 1 1 0.340
0000 0000 X 1 0.054 0 1 0.054
XXXX XXXX X 0 0.000 1 0 0.286
XXXX XXXX X 0 0.000 0 0 0.000
XXXX XXXX X 1 valid 0 1 valid
GND
G
0
G
1
G
2
G
3
G
4
G
5
G
6
G
7
BLANK
V
DD
R
0
GND
NC
R
REF
V
REF
COMP
IO
G
IO
R
V
DD
V
DD
IO
B
GND
GND
NC
GND
R
7
R
6
R
5
R
4
R
3
R
2
R
1
NC
GND
GND
B
0
B
1
B
2
B
3
B
4
B
6
B
5
NC
1
2
3
4
5
6
7
8
9
10
SYNC
11
12
36
35
34
33
32
31
30
29
28
27
CLOCK
26
25
13
14
15
16
17
18
19
20
21
22
B
7
23
24
48
47
46
45
44
43
42
41
40
39
GND
38
37
FMS3810/3815
LQFP Package

FMS3810KRC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Digital to Analog Converters - DAC 100Mhz D/a Converter 8Bit Tripple Video
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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