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LTC2630AHSC6-HM12#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC2630
13
2630ff
timing Diagram
The LTC2630 is a family of single voltage output DACs in
6-lead SC70 packages. Each DAC can operate rail-to-rail
referenced to the input supply, or with its full-scale voltage
set by an integrated reference. Twelve combinations of
accuracy (12-, 10-, and 8-bit), power-on reset value (zero
or mid-scale), and full-scale voltage (2.5V or 4.096V) are
available. The LTC2630 is controlled using a 3-wire SPI/
MICROWIRE compatible interface.
Power-On Reset
The LTC2630-HZ/-LZ clear the output to zero scale when
power is first applied, making system initialization con-
sistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2630
contains circuitry to reduce the power-on glitch: the
analog output typically rises less than 5mV above zero
scale during power on if the power supply is ramped
to 5V in 1ms or more. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See “Power-On Reset Glitch” in the Typical Performance
Characteristics section.
The LTC2630-HM/-LM provide an alternative reset, set-
ting the output to mid-scale
when power is first applied.
SDI
CS/LD
SCK
t
2
t
10
t
5
t
7
t
6
t
1
t
3
t
4
1 2 3 23 24
2630 F01
operation
Transfer Function
The digital-to-analog transfer function is
V
OUT(IDEAL)
=
k
2
N
V
REF
where k is the decimal equivalent of the binary DAC
input code, N is the resolution, and V
REF
is either 2.5V
(LTC2630-L) or 4.096V (LTC2630-H) in internal refer-
ence mode, and V
CC
in Supply as reference mode.
Table 1. Command Codes
Command*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power up) DAC Register
0 0 1 1 Write to and Update (Power up) DAC Register
0 1 0 0 Power down
0 1 1 0 Select Internal Reference (Power-on Reset Default)
0 1 1 1 Select Supply as Reference (V
REF
= V
CC
)
*Command codes not shown are reserved and should not be used.
Figure 1. Serial Interface Timing
LTC2630
14
2630ff
Serial Interface
The CS
/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, enabling the SDI and
SCK buffers and the input shift register. Data (SDI input)
is transferred at the next 24 rising SCK edges. The 4-bit
command, C3-C0, is loaded first; then 4 don’t-care bits;
and finally the 16-bit data word. The data word comprises
the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, fol-
lowed by 4, 6 or 8 don’t-care bits (LTC2630-12, -10 and
-8 respectively; see Figure 2). Data can only be transferred
to the device when the CS
/LD signal is low, beginning on
the first rising edge of SCK. SCK may be high or low at
the falling edge of CS
/LD. The rising edge of CS/LD ends
the data transfer and causes the device to execute the
command specified in the 24-bit input sequence. The
complete sequence is shown in Figure 3a.
operation
The command (C3-C0) assignments are shown in Table 1.
The first three commands in the table consist of write and
update operations. A Write operation loads a 16-bit data
word from the 24-bit shift register into the input register.
In an Update operation, the input register is copied to the
DAC register and converted to an analog voltage at the
DAC output. Write to and Update combines the first two
commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
While the minimum input sequence is 24-bits, it may
optionally be extended to 32-bits to accommodate micro-
processors that have a minimum word width of 16-bits
(2 bytes). To use the 32-bit width, 8 don’t-care bits are
transferred to the device first, followed by the 24-bit se-
quence described. Figure 3b shows the 32-bit sequence.
2630 F02
C3
COMMAND 4 DON'T-CARE BITS
MSB
MSB
MSB
LSB
LSB
LSB
DATA (12 BITS + 4 DON'T-CARE BITS)
C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
C3
COMMAND 4 DON'T-CARE BITS DATA (10 BITS + 6 DON'T-CARE BITS)
C2 C1 C0 X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
C3
COMMAND
INPUT WORD (LTC2630-12)
INPUT WORD (LTC2630-10)
INPUT WORD (LTC2630-8)
4 DON'T-CARE BITS DATA (8 BITS + 8 DON'T-CARE BITS)
C2 C1 C0 X X X X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
Figure 2. Command and Data Input Format
LTC2630
15
2630ff
The 16-bit data word is ignored for all commands that do
not include a Write operation.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplifier, bias circuit, and reference circuit are disabled
and draw essentially zero current. The DAC output is put
into a high-impedance state, and the output pin is passively
pulled to ground through a 200kΩ resistor. Input and DAC
register contents are not disturbed during power-down.
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.8µA
maximum when the DAC is powered down.
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 1. The DAC
is powered up and its voltage output is updated. Normal
settling is delayed while the bias, reference, and amplifier
circuits are re-enabled. The power-up delay time is 18µs
for settling to 12-bits.
Reference Modes
For applications where an accurate external reference is not
available, the LTC2630 has a user-selectable, integrated
reference. The LTC2630-LM and LTC2630-LZ provide
a
full-scale
output of 2.5V. The LTC2630-HM and LTC2630-
HZ provide a full-scale output of 4.096V.
The internal reference can be useful in applications where
the supply voltage is poorly regulated. Internal Reference
mode can be selected by using command 0110, and is
the power-on default.
The DAC can also operate in supply as reference mode
using command 0111. In this mode, V
CC
supplies the
DAC’s reference voltage and the supply current is reduced.
Voltage Output
The LTC2630’s integrated rail-to-rail amplifier has guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage
headroom with
respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Charac-
teristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
operation
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

LTC2630AHSC6-HM12#TRPBF

Mfr. #:
Buy LTC2630AHSC6-HM12#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-bit, 1LSB INL, H-temp, Vout DAC SC70 (4.096V ref, reset to mid-scale)
Lifecycle:
New from this manufacturer.
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