NB7L572MNR4G

© Semiconductor Components Industries, LLC, 2012
June, 2012 Rev. 2
1 Publication Order Number:
NB7L572/D
NB7L572
2.5V / 3.3V Differential 4:1
Mux Input to 1:2 LVPECL
Clock/Data Fanout /
Translator
MultiLevel Inputs w/ Internal Termination
The NB7L572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The
INx/INx inputs includes internal 50 W termination resistors and will
accept differential LVPECL, CML, or LVDS logic levels. The
NB7L572 incorporates a pair of Select pins that will choose one of
four differential inputs and will produce two identical LVPECL output
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, NB7L572 is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The NB7L572 INx/INx inputs, outputs and core logic are powered
by a 2.5 V $5% V or 3.3 V $10% power supply. The two differential
LVPECL outputs will swing 750 mV when externally terminated with
a 50 W resistor to V
CC
2 V, and are optimized for low skew and
minimal jitter.
The NB7L572 is offered in a low profile 5x5 mm 32-pin QFN
Pb-free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB7L572 is a member of the GigaComm family of high
performance clock products.
Features
Input Data Rate > 10.7 Gb/s Typical
Data Dependent Jitter < 15 ps
Maximum Input Clock Frequency > 7 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:2 LVPECL Outputs, < 15 ps max
4:1 MultiLevel Mux Inputs, Accepts LVPECL, CML LVDS
150 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical
Operating Range: V
CC
= 2.375 V to 3.6 V
Internal 50 W Input Termination Resistors
V
REFAC
Reference Output
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN32
MN SUFFIX
CASE 488AM
MARKING
DIAGRAM*
http://onsemi.com
NB7L
572
AWLYYWWG
1
32
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
32
1
0
1
2
3
Q0
Q1
SEL0
SEL1
IN0
IN1
IN2
IN3
IN0
IN1
IN2
IN3
V
REFAC0
V
REFAC1
V
REFAC2
V
REFAC3
V
T0
V
T1
V
T2
V
T3
50W
50W
50W
50W
50W
50W
50W
50W
Q0
Q1
NB7L572
http://onsemi.com
2
Figure 1. Pinout Configuration (Top View)
IN3
VT3
IN3
IN2
VREFAC2
VT2
IN2
IN0
GND
VCC
VT1
NC
VCC
GND
VCC
Q0
Q0
VCC
1
2
3
4
5
6
7
8
VT0
VREFAC0
IN0
IN1
VREFAC1
IN1
9
10
11
12
13
14
15
16
NC
SEL0
VCC
24
23
22
21
20
19
18
17
SEL1
VCC
Q1
Q1
32
31
30
29
28
27
26
25
VREFAC3
Exposed Pad (EP)
NB7L572
Table 1. INPUT SELECT FUNCTION TABLE
SEL1* SEL0* Clock / Data Input Selected
0 0 IN0 Input Selected
0 1 IN1 Input Selected
1 0 IN2 Input Selected
1 1 IN3 Input Selected
*Defaults HIGH when left open.
NB7L572
http://onsemi.com
3
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1, 4
5, 8
25, 28
29, 32
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
LVPECL, CML,
LVDS Input
Noninverted, Inverted, Differential Clock or Data Inputs.
2, 6
26, 30
VT0, VT1
VT2, VT3
Internal 100 W Centertapped Termination Pin for INx / INx
15
18
SEL0
SEL1
LVTTL/LVCMOS
Input
Input Select pins, default HIGH when left open through a 28kW pullup resistor. Input
logic threshold is V
CC
/2. See Select Function, Table 1.
14, 19 NC No Connect
10, 13, 16
17, 20, 23
VCC Positive Supply Voltage. All V
CC
pins must be connected to the positive power supply
for correct DC and AC operation.
11, 12
21, 22
Q0, Q0
Q1, Q1
LVPECL Output Inverted, Noninverted Differential Outputs.
9, 24 GND Negative Supply Voltage, connected to Ground
3
7
27
31
VREFAC0
VREFAC1
VREFAC2
VREFAC3
Output Voltage Reference for CapacitorCoupled Inputs
EP The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heatsinking conduit. The pad is electrically connected to the die, and must be elec-
trically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left
open, and if no signal is applied on INx / INx input, then the device will be susceptible to selfoscillation.
2. All VCC, and GND pins must be externally connected to a power supply for proper operation.

NB7L572MNR4G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution TSMC 4-1-2 MLL-PECL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet