DS1805
Addressable Digital Potentiometer
4 _____________________________________________________________________
Note 1: All voltages are referenced to ground.
Note 2: I
CC
specified with SDA pin open. SCL = 400kHz clock rate.
Note 3: Address inputs A0, A1, and A2 should be connected to either V
CC
or GND, depending on the desired address selections.
Note 4: I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 5: I
STBY
specified with SDA = SCL = V
CC
= 5.0V.
Note 6: Valid at +25°C only.
Note 7: Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position.
Note 8: Relative linearity is used to determine the change in voltage between successive tap positions.
Note 9: -3dB cutoff frequency characteristics for the DS1805 depend on potentiometer total resistance: DS1805-010, 1MHz;
DS1805-50, 200kHz; DS1805-100, 100kHz.
Note 10: A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250ns must then be met. This
will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000ns + 250ns =
1250ns before the SCL line is released.
Note 11: After this period, the first clock pulse is generated.
Note 12: The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN
of the SCL signal)
in order to bridge the undefined region of the falling edge of SCL.
Note 14: C
B
—total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
CC
) and (0.1)(V
CC
).
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V to 5.5V, T
A
= -40°C to +85°C)
