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EVB-EN5367QI

P1-P3P4-P6P7-P8
Enpirion
®
Power Evaluation Board User Guide
EN5367QI PowerSoC
Enpirion EN5367QI DC-DC Converter
w/Integrated Inductor Evaluation Board
Introduction
Thank you for choosing Altera Enpirion power products!
This evaluation board user guide applies to EN5367QI. The EN5367QI is a 6A device.
In addition to this document, you will also need the latest device datasheet.
• The EN5367QI features integrated inductor, power MOSFETS, controller, a bulk
of the compensation network, and protection circuitry against system faults. This
level of integration delivers a substantial reduction in footprint and parts count
over competing solutions. The evaluation board is optimized for engineering ease
of testing through programming options, clip leads, test points etc.
• The EN5367QI features a customer programmable output voltage by means of a
resistor divider. The resistor divider allows the user to set the output voltage to
any value within the range 0.75V to (V
IN
-V
DROPOUT
). The evaluation board, as
shipped is populated with a 4 resistor divider option. The upper resistor is fixed
and has a phase lead capacitor in parallel. One of 4 lower resistors is selected
with the jumper option for different output voltages to change V
OUT
, retain the
upper resistor and capacitor values and change only the lower resistor.
• This device has no over-voltage protection feature. If making modifications to the
board, we strongly recommend the customer to ensure the feedback loop is truly
closed before powering up the device especially if the load can not withstand the
input voltage.
• The input and output capacitors are X5R or X7R multi-layer ceramic chip
capacitors. The Soft-start capacitor is a small 47nF X7R MLCC. Pads are
available to have multiple input and output capacitors. This allows for evaluation
of performance over a wide range of input/output capacitor combinations.
• The jumper labeled LLM/SYNC pin controls the SYNC pin. LLM (light-load mode)
function is not available on this part. This pin should be pulled LOW if the SYNC
function is not to be used. Do not leave this pin floating or high.
• The jumper labeled VDROOP should be left grounded. This function is not
available on this part.
Page 1 of 8
www.altera.com/enpirion
Enpirion
®
Power Evaluation Board User Guide
EN5367QI PowerSoC
• Clip-on terminals are provided for POK, and ENA, pins.
• Banana jacks are provided for V
IN
and V
OUT
power terminals. Several signal and
GND clip-on test points are also provided to measure V
IN
, V
OUT
, and GND nodes.
• A jumper is provided for controlling the Enable signal. Enable may also be
controlled using an external switching source by removing the jumper and
applying the enable signal to the ENA clip-on terminal.
• A jumper is also provided to connect a POK pull-up resistor to the input supply.
This jumper is especially useful to measure the disable current and eliminates
having to subtract the current drawn by the POK resistor.
• Foot print is also provided for a SMA connector to SYNC input. A switching input
to this pin allows the device clock to be phase locked to an external signal. This
external clock synchronization allows for moving any offending beat frequency to
be moved out-of-band. A swept frequency applied to this pin results in spread
spectrum operation and reduces the peaks in the noise spectrum of emitted EMI.
• The board comes with input decoupling and reverse polarity protection to guard
the device against common setup mishaps.
Quick Start Guide
STEP 1: Set the “ENABLE” jumper to the Disable Position, as shown in Figure 1.
Figure 1: Shows POK, Enable, VDROOP and SYNC/LLM Jumpers.
POK PWR jumper as shown connects the pull-up resistor to VIN.
Enable jumper shown is in DISABLE position. SYNC/LLM jumper as
shown ties this pin Low. VDROOP jumper as shown is low, and
should stay grounded.
STEP 2: Connect Power Supply to the input power connectors, VIN (+) and GND (-) as
indicated in Figure 1 and set the supply to the desired voltage. The device disable
current may be measured in this configuration.
CAUTION: be mindful of the polarity. Even though the evaluation board comes with
reverse polarity protection diodes, it may not protect the device under all conditions.
Page 2 of 8
www.altera.com/enpirion
Enpirion
®
Power Evaluation Board User Guide
EN5367QI PowerSoC
STEP 3: Connect the load to the output connectors VOUT (+) and GND (-), as
indicated in Figure 1.
STEP 4: Select the output voltage setting jumper. Figure 2 shows what output voltages
are achieved by selecting each jumper position. Populating multiple jumper positions
will allow you to select higher output voltages. You can populate up to all four jumper
positions for the highest V
OUT
of approximately 3.73V with the resistors populated on the
board.
Figure 2: Output Voltage selection jumpers
Jumper shown selects 1.55V output
(Jumper positions from left to right are: 2.25V, 1.55V, 1.2V and 1.0V)
STEP 5: Set the POK PWR and SYNC/LLM jumpers to desired positions (see Figure 1).
You should disable POK when measuring low value input currents. The SYNC/LLM
jumper should be tied low unless external frequency synchronization is required.
STEP 6: Apply V
IN
to the board and move the ENA jumper to the enabled position. The
EN5367QI is now powered up! Various measurements such as efficiency, line and load
regulation, input / output ripple, load transient, drop-out voltage measurements may be
conducted at this point. The over current trip level, short circuit protection, under voltage
lock out thresholds, temperature coefficient of the output voltage may also be measured
in this configuration.
CAUTION: The maximum allowable VIN for this device is 5.5V.
STEP 6A: Power Up/Down Behavior – Remove ENA jumper and connect a pulse
generator (output disabled) signal to the clip-on test point below ENA and Ground. Set
the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to 10msec. and
duty cycle to 50%. Hook up oscilloscope probes to ENA, POK and VOUT with clean
ground returns. Apply power to evaluation board. Enable pulse generator output.
Observe the VOUT voltage ramps as ENA goes high and again as ENA goes low. The
device when powered down ramps down the output voltage in a controlled manner
before fully shutting down. The output voltage level when POK is asserted /de-asserted
as the device is powered up / down may be observed as well as the clean output
voltage ramp and POK signals.
STEP 7: External Clock Synchronization / Spread Spectrum Modes: In order to
activate this mode, it may be necessary to a solder a SMA connector at J7. Alternately
the input clock signal leads may be directly soldered to the through holes of J7 as
shown below.
Page 3 of 8
www.altera.com/enpirion
P1-P3P4-P6P7-P8

EVB-EN5367QI

Mfr. #:
Buy EVB-EN5367QI
Manufacturer:
Intel / Altera
Description:
Power Management IC Development Tools EN5367QI EVAL 6A DC/DC BUCK
Lifecycle:
New from this manufacturer.
Delivery:
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