4
LTC1430
G1 (Pin 1/Pin 1): Driver Output 1. Connect this pin to the
gate of the upper N-channel MOSFET, M1. This output will
swing from PV
CC1
to PGND. It will always be low when G2
is high.
PV
CC1
(Pin 2/Pin 2): Power V
CC
for Driver 1. This is the
power supply input for G1. G1 will swing from PGND to
PV
CC1
. PV
CC1
must be connected to a potential of at least
PV
CC
+ V
GS(ON)
(M1). This potential can be generated
using an external supply or a simple charge pump con-
nected to the switching node between the upper MOSFET
and the lower MOSFET; see Applications Information for
details.
PGND (Pin 3/Pin 3): Power Ground. Both drivers return to
this pin. It should be connected to a low impedance ground
in close proximity to the source of M2. 8-lead parts have
PGND and GND tied together at pin 3.
GND (Pin 4/Pin 3): Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, GND should be connected to
PGND right at the LTC1430. 8-lead parts have PGND and
GND tied together internally at pin 3.
SENSE
, FB, SENSE
+
(Pins 5, 6, 7/Pin 4): These three
pins connect to the internal resistor divider and to the
internal feedback node. To use the internal divider to set
the output voltage to 3.3V, connect SENSE
+
to the positive
terminal of the output capacitor and SENSE
to the nega-
tive terminal. FB should be left floating in applications that
use the internal divider. To use an external resistor divider
to set the output voltage, float SENSE
+
and SENSE
and
connect the external resistor divider to FB.
SHDN (Pin 8/Pin 5): Shutdown. A TTL compatible low
level at SHDN for longer than 50µs puts the LTC1430 into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally.
SS (Pin 9/NA): Soft-Start. The SS pin allows an external
capacitor to be connected to implement a soft-start func-
tion. An external capacitor from SS to ground controls the
start-up time and also compensates the current limit loop,
allowing the LTC1430 to enter and exit current limit
cleanly. See Applications Information for more details.
COMP (Pin 10/Pin 6): External Compensation. The COMP
pin is connected directly to the output of the error amplifier
and the input of the PWM. An RC network is used at this
node to compensate the feedback loop to provide opti-
mum transient response. See Applications Information for
compensation details.
FREQSET (Pin 11/NA): Frequency Set. This pin is used to
set the free running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 200kHz.
A resistor from FREQSET to ground will speed up the
oscillator; a resistor to V
CC
will slow it down. See Applica-
tions Information for resistor selection details.
I
MAX
(Pin 12/NA): Current Limit Set. I
MAX
sets the thresh-
old for the internal current limit comparator. If I
FB
drops
below I
MAX
with G1 on, the LTC1430 will go into current
limit. I
MAX
has a 12µA pull-down to GND. It can be adjusted
with an external resistor to PV
CC
or an external voltage
source.
I
FB
(Pin 13/NA): Current Limit Sense. Connect to the
switched node at the source of M1 and the drain of M2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging I
FB
. This pin can be
taken up to 18V above GND without damage.
V
CC
(Pin 14/Pin 7): Power Supply. All low power internal
circuits draw their supply from this pin. Connect to a clean
power supply, separate from the main PV
CC
supply at the
drain of M1. This pin requires a 4.7µF bypass capacitor.
8-lead parts have V
CC
and PV
CC2
tied together at pin 7 and
require a 10µF bypass to GND.
PV
CC2
(Pin 15/Pin 7): Power V
CC
for Driver 2. This is the
power supply input for G2. G2 will swing from GND to
PV
CC2
. PV
CC2
is usually connected to the main high power
supply. The 8-lead parts have V
CC
and PV
CC2
tied together
at pin 7 and require a 10µF bypass to GND.
G2 (Pin 16/Pin 8): Driver Output 2. Connect this pin to the
gate of the lower N-channel MOSFET, M2. This output will
swing from PV
CC2
to PGND. It will always be low when G1
is high.
(16-Lead Package/8-Lead Package)
PI FU CTIO S
UUU
5
LTC1430
+
+
I
LIM
FB MIN
PWM
MAX
+
40mV
20.1k
+
1.26V
12µA
+
40mV
12µA
12.4k
PV
CC1
SHDN
FREQSET
COMP
SS
I
MAX
V
CC
PV
CC2
G1
G2
PGND
I
FB
FB
SENSE
+
SENSE
LTC1430 • BD
INTERNAL
SHUTDOWN
50µs
DELAY
BLOCK DIAGRA
W
Figure 1
Figure 2
Figure 3
LTC1430
PV
CC1
5V
V
CC
PV
CC2
GND
PGND
G1 RISE/FALL
G2 RISE/FALL
G1
G2
10,000pF
LTC1430 • TC03
10,000pF
10µF 0.1µF
SHDN
V
SHDN
I
MAX
FREQSET
COMP
SS
NC
NC
NC
NC
V
CC
PV
CC2
LTC1430
PV
CC
PV
CC1
I
FB
GND PGND SENSE
+
SENSE
LTC1430 • TC02
G1
G2
FB
NC
NC
NC
V
CC
+
C
IN
220µF
×4
C
OUT
330µF
×6
+
+
+
2.7µH/15A
PV
CC1
V
CC
FREQSET
SHDN
COMP
SS
PV
CC2
PV
CC
= 5V
PGND
GND
G1
I
FB
I
MAX
G2NC
LTC1430 • F01
SHUTDOWN
FB NC
SENSE
+
LTC1430
SENSE
1.61k
1k
FB
NC
NC
SENSE
+
SENSE
LTC1430
FB MEASUREMENT
V
OUT
100
R
C
7.5k
C
C
4700pF
C1
220pF
1N4148
1µF
0.01µF
0.1µF
4.7µF
0.1µF
3.3V
M1A, M1B
2 IN PARALLEL
M2
M1A, M1B, M2: MOTOROLA MTD20N03HL
C
IN
: AVX-TPSE227M010R0100
C
OUT
: AVX-TPSE337M006R0100
TEST CIRCUITS
6
LTC1430
OVERVIEW
The LTC1430 is a voltage feedback PWM switching regu-
lator controller (see Block Diagram) designed for use in
high power, low voltage step-down (buck) converters. It
includes an onboard PWM generator, a precision refer-
ence trimmed to ±0.5%, two high power MOSFET gate
drivers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 200kHz.
The 16-lead versions of the LTC1430 include a current
limit sensing circuit that uses the upper external power
MOSFET as a current sensing element, eliminating the
need for an external sense resistor.
Also included in the 16-lead version is an internal soft-
start feature that requires only a single external capacitor
to operate. In addition, 16-lead parts feature an adjustable
oscillator which can run at frequencies from 50kHz to
beyond 500kHz, allowing added flexibility in external com-
ponent selection. The 8-lead versions do not include
current limit, internal soft-start or frequency adjustability.
THEORY OF OPERATION
Primary Feedback Loop
The LTC1430 senses the output voltage of the circuit at the
output capacitor with the SENSE
+
and SENSE
pins and
feeds this voltage back to the internal transconductance
amplifier FB. FB compares the resistor-divided output
voltage to the internal 1.26V reference and outputs an
error signal to the PWM comparator. This is then com-
pared to a fixed frequency sawtooth waveform generated
by the internal oscillator to generate a pulse width modu-
lated signal. This PWM signal is fed back to the external
MOSFETs through G1 and G2, closing the loop. Loop
compensation is achieved with an external compensation
network at COMP, the output node of the FB transconduc-
tance amplifier.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the FB
amplifier may not respond quickly enough. MIN compares
the feedback signal to a voltage 40mV (3%) below the
internal reference. At this point, the MIN comparator
overrides the FB amplifier and forces the loop to full duty
cycle, set by the internal oscillator at about 90%. Similarly,
the MAX comparator monitors the output voltage at 3%
above the internal reference and forces the output to 0%
duty cycle when tripped. These two comparators prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.
Current Limit Loop
The 16-lead LTC1430 devices include yet another feed-
back loop to control operation in current limit. The current
limit loop is disabled in 8-lead devices. The I
LIM
amplifier
monitors the voltage drop across external MOSFET M1
with the I
FB
pin during the portion of the cycle when G1 is
high. It compares this voltage to the voltage at the I
MAX
pin.
As the peak current rises, the drop across M1 due to its
R
DS(ON)
increases. When I
FB
drops below I
MAX
, indicating
that M1’s drain current has exceeded the maximum level,
I
LIM
starts to pull current out of the external soft-start
capacitor, cutting the duty cycle and controlling the output
current level. At the same time, the I
LIM
comparator
generates a signal to disable the MIN comparator to
prevent it from conflicting with the current limit circuit. If
the internal feedback node drops below about 0.8V, indi-
cating a severe output overload, the circuitry will force the
internal oscillator to slow down by a factor of as much as
100. If desired, the turn on time of the current limit loop
can be controlled by adjusting the size of the soft-start
capacitor, allowing the LTC1430 to withstand short over-
current conditions without limiting.
By using the R
DS(ON)
of M1 to measure the output current,
the current limit circuit eliminates the sense resistor that
would otherwise be required and minimizes the number of
components in the external high current path. Because
power MOSFET R
DS(ON)
is not tightly controlled and varies
with temperature, the LTC1430 current limit is not de-
signed to be accurate; it is meant to prevent damage to the
power supply circuitry during fault conditions. The actual
current level where the limiting circuit begins to take effect
may vary from unit to unit, depending on the power
MOSFETs used. See Soft-Start and Current Limit for more
details on current limit operation.
APPLICATIO S I FOR ATIO
WUU
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LTC1430CS#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Pwr Buck Sw Reg Cntr
Lifecycle:
New from this manufacturer.
Delivery:
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