LT6013/LT6014
13
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APPLICATIO S I FOR ATIO
WUUU
Preserving Input Precision
Preserving the input accuracy of the
LT6013 and
LT6014
requires that the applications circuit and PC board layout
do not introduce errors comparable to or greater than the
10µV typical offset of the amplifiers. Temperature differen-
tials across the input connections can generate thermo-
couple voltages of 10’s of microvolts so the connections
to the input leads should be short, close together and away
from heat dissipating components. Air currents across the
board can also generate temperature differentials.
The extremely low input bias currents allow high accuracy
to be maintained with high impedance sources and feed-
back resistors. The LT6013 and LT6014 low input bias cur-
rents are obtained by a cancellation circuit on-chip. This
causes the resulting I
B
+
and I
B
to be uncorrelated, as
implied by the I
OS
specification being comparable to I
B
. Do
not try to balance the input resistances in each input lead;
instead keep the resistance at either input as low as pos-
sible for maximum accuracy.
Leakage currents on the PC board can be higher than the
input bias current. For example, 10G of leakage between
a 15V supply lead and an input lead will generate 1.5nA!
Surround the input leads with a guard ring driven to the
same potential as the input common mode to avoid exces-
sive leakage in high impedance applications.
Input Protection
The LT6013/LT6014 features on-chip back-to-back diodes
between the input devices, along with 500 resistors in
series with either input. This internal protection limits the
input current to approximately 10mA (the maximum al-
lowed) for a 10V differential input voltage. Use additional
external series resistors to limit the input current to 10mA
in applications where differential inputs of more than 10V
are expected. For example, a 1k resistor in series with each
input provides protection against 30V differential voltage.
Input Common Mode Range
The LT6013/LT6014 output is able to swing close to each
power supply rail (rail-to-rail out), but the input stage is
limited to operating between V
+ 1V and V
+
– 1.2V. Exceed-
ing this common mode range will cause the gain to drop
to zero; however, no phase reversal will occur.
Total Input Noise
The LT6013 and LT6014 amplifiers contribute negligible
noise to the system when driven by sensors (sources) with
impedance between 10k and 1M. Throughout this
range, total input noise is dominated by the 4kTR
S
noise
of the source. If the source impedance is less than 10k,
the input voltage noise of the amplifier starts to contribute
with a minimum noise of 9.5nV/Hz for very low source im-
pedance. If the source impedance is more than 1M, the
input current noise of the amplifier, multiplied by this high
impedance, starts to contribute and eventually dominate.
Total input noise spectral density can be calculated as:
v e kTR i R
n TOTAL n S n S()
()=+ +
2
2
4
where e
n
= 9.5nV/Hz , i
n
= 0.15pA/Hz and R
S
is the total
impedance at the input, including the source impedance.
Capacitive Loads
The LT6013 and LT6014 can drive capacitive loads up to
500pF at a gain of 5. The capacitive load driving capability
increases as the amplifier is used in higher gain configu-
rations. A small series resistance between the output and
the load further increases the amount of capacitance that
the amplifier can drive.
LT6013/LT6014
14
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SI PLIFIED SCHE ATIC
WW
60134 SS
Q22
Q16
Q3
Q7
Q8
C
B
A
B
A
Q15
V
+
V
Q1 Q2
D2D1
Q11
Q17
Q21
Q4
Q6
Q5
C2
Q12
D3
D4
D5
Q14
Q20
Q19
Q13
Q18
R3 R4
R6
R5
R
C1
R1
500
R2
500
C1
C3
+IN
–IN
OUT
Q9
Q10
(One Amplifier)
LT6013/LT6014
15
60134fb
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)
× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1
2
3
4
.150 – .157
(3.810 – 3.988)
NOTE 3
8
7
6
5
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN
.160
±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT6013ACDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers 1x 145 A, 9.5nV/rtHz, AV >=5, R2R Out P
Lifecycle:
New from this manufacturer.
Delivery:
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