RT9013
7
DS9013-10 April 2011 www.richtek.com
PSRR
-70
-60
-50
-40
-30
-20
-10
0
10
20
10 100 1000 10000 100000 1000000
Frequency (Hz)
PSRR(dB)
I
LOAD
= 100mA
I
LOAD
= 300mA
I
LOAD
= 10mA
V
IN
= 2.5V to 2.6V
V
IN
= 3.0V (By Battery), I
LOAD
= 300mA
Noise
Time (10ms/Div)
Noise (μV/Div)
300
200
100
0
-100
-200
-300
RT9013-15PQW
RT9013
8
DS9013-10 April 2011www.richtek.com
Applications Information
Like any low-dropout regulator, the external capacitors used
with the RT9013 must be carefully selected for regulator
stability and performance. Using a capacitor whose value
is > 1μF/X7R on the RT9013 input and the amount of
capacitance can be increased without limit. The input
capacitor must be located a distance of not more than 0.5
inch from the input pin of the IC and returned to a clean
analog ground. Any good quality ceramic can be used for
this capacitor. The capacitor with larger value and lower
ESR (equivalent series resistance) provides better PSRR
and line-transient response.
The output capacitor must meet both requirements for
minimum amount of capacitance and ESR in all LDOs
application. The RT9013 is designed specifically to work
with low ESR ceramic output capacitor in space-saving
and performance consideration. Using a ceramic capacitor
whose value is at least 1μF with ESR is > 5mΩ on the
RT9013 output ensures stability. The RT9013 still works
well with output capacitor of other types due to the wide
stable ESR range. Figure 1. shows the curves of allowable
ESR range as a function of load current for various output
capacitor values. Output capacitor of larger capacitance
can reduce noise and improve load transient response,
stability, and PSRR. The output capacitor should be located
not more than 0.5 inch from the VOUT pin of the RT9013
and returned to a clean analog ground.
Figure 1
Enable
The RT9013 goes into sleep mode when the EN pin is in a
logic low condition. During this condition, the RT9013 has
an EN pin to turn on or turn off regulator, When the EN pin
is logic hight, the regulator will be turned on. The supply
current to 0.7μA typical. The EN pin may be directly tied
to V
IN
to keep the part on. The Enable input is CMOS
logic and cannot be left floating.
PSRR
The power supply rejection ratio (PSRR) is defined as the
gain from the input to output divided by the gain from the
supply to the output. The PSRR is found to be
×=
ΔSupply
Error ΔGain
log20 PSRR
Note that when heavy load measuring, Δsupply will cause
Δtemperature. And Δtemperature will cause Δoutput
voltage. So the heavy load PSRR measuring is include
temperature effect.
Current limit
The RT9013 contains an independent current limiter, which
monitors and controls the pass transistor's gate voltage,
limiting the output current to 0.6A (typ.). The output can
be shorted to ground indefinitely without damaging the part.
Thermal Considerations
Thermal protection limits power dissipation in RT9013.
When the operation junction temperature exceeds 170°C,
the OTP circuit starts the thermal shutdown function and
turns the pass element off. The pass element turn on again
after the junction temperature cools by 30°C.
For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The
power dissipation definition in device is :
P
D
= (V
IN
V
OUT
) x I
OUT
+ V
IN
x I
Q
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
Region of Stable C
OUT
ESR vs. Load Current
0.001
0.010
0.100
1.000
10.000
100.000
0 50 100 150 200 250 300
Load Current (mA)
C
OUT
ESR
()
Region of Stable C
OUT
ESR (Ω)
C
OUT
= 1μF
Stable Range
Unstable Range
Unstable Range
100
0
1
0.1
0.01
0.001
RT9013
9
DS9013-10 April 2011 www.richtek.com
Figure 2. Derating Curves for RT9013 Packages
P
D(MAX)
= ( T
J(MAX)
T
A
) /θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature, T
A
is the ambient temperature and the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT9013 the maximum junction temperature is 125°C and
T
A
is the operated ambient temperature. The junction to
ambient thermal resistance θ
JA
(θ
JA
is layout dependent)
for WDFN-6L 2x2 package is 165°C/W, SOT-23-5 package
is 250°C/W and SC-70-5/ SC-82 package is 333°C/W on
the standard JEDEC 51-3 single-layer thermal test board.
The maximum power dissipation at T
A
= 25°C can be
calculated by following formula :
P
D(MAX)
= (125°C 25°C) / 165°C/W = 0.606 W for
WDFN-6L 2x2 packages
P
D(MAX)
= (125°C 25°C) / 250°C/W = 0.400 W for
SOT-23-5 packages
P
D(MAX)
= (125°C 25°C) / 333°C/W = 0.300 W for
SC-70-5/ SC-82 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal resistance
θ
JA
. For RT9013 package, the Figure 2 of derating curves
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation allowed.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 12.5 25 37.5 50 62.5 75 87.5 100 113 125
Ambient Temperature
Power Dissipation (W)
(°C)
Single Layer PCB
WDFN-6L 2x2
SOT-23-5
SC-70-5/
SC-82

RT9013-33GB

Mfr. #:
Manufacturer:
Description:
IC REG LINEAR 3.3V 500MA SOT23-5
Lifecycle:
New from this manufacturer.
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