© Semiconductor Components Industries, LLC, 2012
October, 2012 Rev. 0
1 Publication Order Number:
CAV25128/D
CAV25128
128-Kb SPI Serial CMOS
EEPROM
Description
The CAV25128 is a 128Kb Serial CMOS EEPROM device
internally organized as 16Kx8 bits. This features a 64byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS
) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD
input may be used to pause any serial
communication with the CAV25128 device. The device features
software and hardware write protection, including partial as well as
full array protection.
OnChip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
Automotive Temperature Grade 1 (40°C to +125°C)
10 MHz SPI Compatible
2.5 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
64byte Page Write Buffer
Additional Identification Page with Permanent Write Protection
Selftimed Write Cycle
Hardware and Software Protection
Block Write Protection
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
8Lead SOIC and TSSOP Packages
This Device is PbFree, Halogen Free/BFR Free, and RoHS
Compliant
SI
SOCAV25128
SCK
V
SS
V
CC
CS
WP
HOLD
Figure 1. Functional Symbol
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PIN CONFIGURATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
SOIC8
V SUFFIX
CASE 751BD
SOIC (V), TSSOP (Y)
TSSOP8
Y SUFFIX
CASE 948AL
Chip SelectCS
Serial Data OutputSO
Write ProtectWP
GroundV
SS
Serial Data InputSI
Serial ClockSCK
FunctionPin Name
PIN FUNCTION
Hold Transmission InputHOLD
Power SupplyV
CC
SI
HOLD
V
CC
V
SS
WP
SO
CS
1
SCK
CAV25128
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2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Operating Temperature 45 to +130 °C
Storage Temperature 65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than 1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter Min Units
N
END
(Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, T
A
= 40°C to +125°C, unless otherwise specified.)
Symbol
Parameter Test Conditions Min Max Units
I
CCR
Supply Current (Read Mode) Read, SO open, f
SCK
= 10 MHz 2 mA
I
CCW
Supply Current (Write Mode) Write, CS = V
CC
2 mA
I
SB1
Standby Current V
IN
= GND or V
CC
, CS = V
CC
,
WP
= V
CC
, V
CC
= 5.5 V
3
mA
I
SB2
Standby Current V
IN
= GND or V
CC
, CS = V
CC
,
WP
= GND, V
CC
= 5.5 V
5
mA
I
L
Input Leakage Current V
IN
= GND or V
CC
2 2
mA
I
LO
Output Leakage Current CS = V
CC
V
OUT
= GND or V
CC
2 2
mA
V
IL
Input Low Voltage 0.5 0.3 V
CC
V
V
IH
Input High Voltage 0.7 V
CC
V
CC
+ 0.5 V
V
OL
Output Low Voltage I
OL
= 3.0 mA 0.4 V
V
OH
Output High Voltage I
OH
= 1.6 mA V
CC
0.8 V V
Table 4. PIN CAPACITANCE (Note 5) (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
Test Conditions Min Typ Max Units
C
OUT
Output Capacitance (SO) V
OUT
= 0 V 8 pF
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD) V
IN
= 0 V 8 pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
CAV25128
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3
Table 5. A.C. CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, T
A
= 40°C to +125°C, unless otherwise specified.) (Note 6)
Symbol
Parameter Min Max Units
f
SCK
Clock Frequency DC 10 MHz
t
SU
Data Setup Time 10 ns
t
H
Data Hold Time 10 ns
t
WH
SCK High Time 40 ns
t
WL
SCK Low Time 40 ns
t
LZ
HOLD to Output Low Z 25 ns
t
RI
(Note 7) Input Rise Time 2
ms
t
FI
(Note 7) Input Fall Time 2
ms
t
HD
HOLD Setup Time 0 ns
t
CD
HOLD Hold Time 10 ns
t
V
Output Valid from Clock Low 40 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 20 ns
t
HZ
HOLD to Output High Z 25 ns
t
CS
CS High Time 40 ns
t
CSS
CS Setup Time 30 ns
t
CSH
CS Hold Time 30 ns
t
CNS
CS Inactive Setup Time 20 ns
t
CNH
CS Inactive Hold Time 20 ns
t
WPS
WP Setup Time 10 ns
t
WPH
WP Hold Time 10 ns
t
WC
(Note 8) Write Cycle Time 5 ms
6. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times: 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL
max
/I
OH
max
; C
L
= 30 pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 6. POWERUP TIMING (Notes 7, 9)
Symbol Parameter Min Max Units
t
PUR
Powerup to Read Operation 0.1 1 ms
t
PUW
Powerup to Write Operation 0.1 1 ms
9. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.

CAV25128YE-GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 128KB SPI SER CMOS EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
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