NCP1562A, NCP1562B
http://onsemi.com
22
The SYNC pin is in a high impedance mode during the
charging of the RTCT Ramp. In this period the oscillator
accepts an external SYNC pulse. If no pulse is detected
upon reaching the peak of the RTCT Ramp, a 100 ns SYNC
pulse is generated. The SYNC pulse is gene rated by
internally pulling the SYNC pin to V
REF
. The peak voltage
of the SYNC pin is typically 4.3 V. Once the 100 ns timer
expires, the pin goes back into a high impedance mode and
an external resistor is required for pull down as shown in
Figure 49.
V
REF
RTCT
SYNC
R
SYNC
C
T
R
T
Figure 49. SYNC Pulse
The slew rate of the sync pin is determined by t he pin
capacitance and external pulldown resistor. The maximum
source curre nt of the SYNC pin i s 1.0 mA. The resistor is
sized to allow the SYNC pin to discharge before the start
of the ne xt cycle.
If an external pulse is received on the SYNC pin before
the internal pulse is generated, the controller enters the
slave mode of operation. Once opera tion in slave mode
commences, C
T
begins discharging and t he R
T
C
T
Ramp
upper thre shold is increased to 4.0 V.
If a controller in slave mode doe s not receive a sync pulse
before reaching the R
T
C
T
Ramp pe ak voltage (4.0 V), the
upper threshold is reset back to 3.0 V and the converter
reverts to operation in master mode. To guarantee the
converter stays in slave mode, the minimum clock period
of the master controller has to be less than the R
T
C
T
charge
time from 2.0 V to 4.0 V.
Two NCP1562’s are synchronized by connecting their
SYNC pins togethe r. The first device t hat ge nerates a sync
pulse duri ng powerup become s the master. A diode
connec ted as shown in Figure 50 can be used to
perma nently set one controller as the master. The diode
prevents the master from receiving the SYNC pulse of the
slave controller.
MASTER
CONTROLLER
SLAVE
CONTROLLER
SYNC
R
SYNC1
R
SYNC2
SYNC
Figure 50. Master--Slave Configuration
5.0 V Reference
The NCP1562 has a precision 5.0 V reference output. It
is a buffered version of the internal reference. The 5.0 V
refere nce i s biased directly from V
AUX
and it can supply up
to 5.0 mA. Load regulation is 50 mV and line regulation is
100 mV within the specified operating range.
It is required to bypass the reference with a capacitor.
The capacitor is used for compensation of the internal
regulator and high frequency noise filtering. The capacitor
should be placed across the V
REF
and GND pins. In most
applications a 0.1 mF will suffice. A bigger capacitor may
be require d to re duce the volt age ripple ca used by the
oscillator current. The recommended capacitor range is
betwee n 0.047 mF and 1. 0 mF.
During powerup, the 5.0 V reference is enabled once
V
AUX
reaches V
AUX(on)
and a UV fault is not present.
Otherwise, the reference is enabled once the UV fault is
removed and V
AUX
reaches V
AUX(on)
.
Once a UV fault is detected after the reference has been
enabled, the reference is disabled after the soft--stop
sequence is complete if the UV fault is still present. If the
UV fault is removed before soft--stop is complete, the
refere nce is not disabled.
Application Information
ON Semiconductor provides an electronic design tool, a
demonstration board and an application note to facilitate
design of the NCP1562 and reduce development cycle
time. All the tools can be downloaded or ordered at
www.onsemi.com.
The electronic design tool allows the user to easily
determine most of the system parameters of an active
clamp forward converter. The tool evaluates the power and
active clamp stage s as well as the frequency response of the
system. The tool is used to design a converter for a 48 V
telecom system. The converter delivers 100 W at 3.3 V.
The circuit schematic is shown in Figure 51. The converte r
design is described in Application Note AND8273/D.
