13 www.fairchildsemi.com
MM74HC4046
Detailed Circuit Description (Continued)
If the VCO leads the signal then when the leading edge of
the VCO is seen the output of the phase comparator goes
LOW. This discharges the loop filter until the leading edge
of the signal is detected at which time the output 3-STATE
itself again. This has the effect of slowing down the VCO to
again make the rising edges of both waveform coincident.
When the PLL is out of lock the VCO will be running either
slower or faster than the signal input. If it is running slower
the phase detector will see more signal rising edges and so
the output of the phase comparator will be HIGH a majority
of the time, raising the VCO’s frequency. Conversely, if the
VCO is running faster than the signal the output of the
detector will be LOW most of the time and the VCO’s out-
put frequency will be decreased.
As one can see when the PLL is locked the output of phase
comparator II will be almost always 3-STATE except for
minor corrections at the leading edge of the waveforms.
When the detector is 3-STATE the phase pulse output is
HIGH. This output can be used to determine when the PLL
is in the locked condition.
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase differ-
ence between the comparator input and the signal input.
The lock range of the PLL is the same as the capture
range. Minimal power is consumed in the loop filter since in
lock the detector output is a high impedance. Also when no
signal is present the detector will see only VCO leading
edges, and so the comparator output will stay LOW forcing
the VCO to f
MIN
operating frequency.
Phase comparator II is more susceptible to noise causing
the phase lock loop to unlock. If a noise pulse is seen on
the signal input, the comparator treats it as another positive
edge of the signal and will cause the output to go HIGH
until the VCO leading edge is seen, potentially for a whole
signal input period. This would cause the VCO to speed up
during that time. When using the phase comparator I the
output of that phase detector would be disturbed for only
the short duration of the noise spike and would cause less
upset.
PHASE COMPARATOR III
This comparator is a simple S-R Flip-Flop which can func-
tion as a phase comparator Figure 8. It has some similar
characteristics to the edge sensitive comparator. To see
how this detector works assume input pulses are applied to
the signal and comparator inputs as shown in Figure 9.
When the signal input leads the comparator input the flop is
set. This will charge up the loop filter and cause the VCO to
speed up, bringing the comparator into phase with the sig-
nal input. When using short pulses as input this comparator
behaves very similar to the second comparator. But one
can see that if the signal input is a long pulse, the output of
the comparator will be forced to a one no matter how many
comparator input pulses are received. Also if the VCO input
is a square wave (as it is) and the signal input is pulse then
the VCO will force the comparator output LOW much of the
time. Therefore it is ideal to condition the signal and com-
parator input to short pulses. This is most easily done by
using a series capacitor.
FIGURE 8. Phase Comparator III Logic Diagram
FIGURE 9. Typical Waveforms for Phase Comparator III
