NBSG86A
www.onsemi.com
10
Table 13. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
Symbo
Characteristic
−40°C 25°C 85°C
Uni
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Input Clock Frequency
(See Figure 7) (Note 26)
7 8 7 8 7 8 GHz
V
OUTPP
Output Voltage Amplitude f
in
v 7 GHz
(OLS = V
CC
)f
in
= 8 GHz
590
270
730
440
470
230
720
420
540
180
700
390
mV
mV
t
PLH
,
t
PHL
Propagation Delay to Output Differential
(Figure 16) D/SEL → Q
110 160 210 115 165 215 120 170 220
ps
t
SKEW
Duty Cycle Skew (Note 27) 5 15 5 15 5 15 ps
t
SKEW
Channel Skew Q → D/SEL 5 20 5 20 5 20 ps
t
S
Set−Up Time (Dx to SEL) 30 30 30 ps
t
H
Hold−Up Time (Dx to SEL) 35 35 35 ps
t
JITTER
RMS Random Clock Jitter
(See Figure 7) (Note 29)
f
in
v 7 GHz
Peak−to−Peak Data Dependent Jitter
(Note 30) f
in
v 7 Gb/s
0.5
12
1.5 0.5
12
1.5 0.5
12
1.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75 2600 75 2600 75 2600 mV
t
r
t
f
Output Rise/Fall Times (20% − 80%) (Q, Q)
t
r
@ 1 GHz t
f
30
17
45
35
60
65
30
17
45
35
60
65
30
17
45
35
60
65
ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
26.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to V
CC
− 2.0 V. Input edge rates 40 ps (20% − 80%).
27.t
SKEW
= |t
PLH
− t
PHL
| for a nominal 50% differential clock input waveform. See Figure 16.
28.V
INPP
(max) cannot exceed V
CC
− V
EE
.
29.Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
30.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2
31
−1 data rate at 7 Gb/s.
