DS1881Z-050+ Datasheet DS1881Z-050+, DS1881E-050+ | P10-P12

DS1881

Dual NV Audio Taper Digital Potentiometer

10 ____________________________________________________________________

Potentiometer Wiper Setting

If 00 or 01 are the values of the two MSBs of the

Command Byte, then the wiper settings of the poten-

tiometers are to be programmed. The lower 6 LSBs of

the Command Byte are then used to store the wiper

settings for the selected potentiometer. See below for

the potentiometer wiper setting details.

POTENTIOMETER WIPER REGISTER

Factory Default: XX111111b

Memory Type: NV (EEPROM)

0 X WIPER SETTING

b7 b6 b5 b4 b3 b2 b1 b0

bits 7, 6

Configuration Selection: Selects which potentiometer will be programmed.

00 = Potentiometer 0 will be programmed.

01 = Potentiometer 1 will be programmed.

bits 5–0

These bits determine the wiper setting of the selected potentiometer. Available wiper settings are determined by

the attenuation option as described in the Configuration Register section.

DS1881

Dual NV Audio Taper Digital Potentiometer

____________________________________________________________________ 11

Configuration Register

If 10 is entered as the value of the two MSBs of the

Command Byte, then the Configuration Register is to

be modified. The three LSBs of the Configuration

crossing detection feature, and the potentiometer atten-

uation configuration.

CONFIGURATION REGISTER

Factory Default: 87h

Memory Type: NV (EEPROM)

1 0 X X X

V/NV

CONTROL

ZERO-

CROSSING

POT

CONFIG

b7 b6 b5 b4 b3 b2 b1 b0

bits 7, 6

Configuration Selection: When bit 7 is set to a 1 and bit 6 is set to a 0, the following configuration bits can be set

and stored in EEPROM.

bits 5, 4, 3 These bits have no function.

bit 2

Volatile/Nonvolatile Potentiometer Register Control Bit: A control bit that sets the potentiometer registers to be

either volatile or nonvolatile memory.

0 = Potentiometer registers are set to nonvolatile memory storage.

1 = Potentiometer registers are set to volatile memory storage. On power-up, the potentiometer wipers are in the

mute position (default).

bit 1

Zero-Crossing Detection Enable Bit: A bit used to enable and disable the zero-crossing functionality.

0 = Zero-crossing detection is disabled.

1 = Zero-crossing detection is enabled (default).

bit 0

Potentiometer Position Configuration: A control bit used to select the number of positions both potentiometers

have.

0 = Potentiometers have 63 positions and mute.

1 = Potentiometers have 33 positions and mute (default).

DS1881

Dual NV Audio Taper Digital Potentiometer

12 ____________________________________________________________________

C Interface for the DS1881

The CE pin serves as a communication enable pin.

When active (CE = 0), the inputs SDA and SCL are rec-

ognized by the device. If inactive (CE = 1), pins SDA

and SCL are disabled, making I

C communication

impossible.

Three pins, A0, A1, A2, serve as slave address inputs.

For multidrop configurations, they allow eight such

devices to be addressed by the same I

C bus. If the

C address matches the hardware levels of these bits,

the DS1881 is allowed to receive communications from

the I

C bus.

The I

C slave address byte is shown below. This is the

first byte transmitted from the master to the DS1881.

The upper nibble value is fixed to 0101. Bit values A2,

A1, and A0 are determined by the states of the corre-

sponding pins. The LSB, R/W, determines whether a

read or write will be performed.

The next byte to be transmitted is the Command Byte

(see the Command Byte section for details).

READ PROTOCOL

MSB LSB

POT-0 10

MSB LSB

POT-1

11010

MSB LSB

R/W = 1

DATA BYTES ARE READ IN THE ORDER SHOWN ABOVE.

COMMAND

BYTE

COMMAND

BYTE

COMMAND

BYTE

SLAVE ADDRESS

BYTE

MSB LSB

CONFIG

REG

START

ACK

STOP

Figure 1. Read Protocol

SLAVE ADDRESS BYTE

0 1 0 1 A2A1A0R/W

MSB LSB

Reading Pot Values

As shown in Figure 1, the DS1881 provides one read

command operation. This operation allows the user to

read both Potentiometer Wiper Setting Registers and

the Configuration Register. To initiate a read operation,

the R/W bit of the slave address byte is set to 1.

Communication to read the DS1881 begins with a

START condition, which is issued by the master device.

The slave address byte sent from the master device fol-

lows the START condition. Once a matching slave

address byte has been received by the DS1881, the

DS1881 responds with an acknowledge. The master

can then begin to receive data. The value of the wiper

of Potentiometer 0 is the first returned from the DS1881.

It is then followed by the value of Potentiometer 1 and

then the value of the Configuration Register. Once the 8

bits of the Configuration Register have been sent, the

master needs to issue an acknowledge, unless it is the

last byte to be read, in which case the master issues a

not acknowledge. If desired, the master may stop the

communication transfer at this point by issuing the

STOP condition after the not acknowledge. However, if

the value of the three registers is needed again, the

transfer can continue by clocking the 8 bits of the

Potentiometer 0 value as described above.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

DS1881Z-050+

Mfr. #:

Buy DS1881Z-050+

Manufacturer:

Maxim Integrated

Description:

Digital Potentiometer ICs Dual NV Audio Tape

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DS1881Z-050+

DS1881Z-050+

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