NLSX5011
www.onsemi.com
10
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
The NLSX5011 auto−sense translator provides
bi−directional logic voltage level shifting to transfer data
in multiple supply voltage systems. These level translators
have two supply voltages, V
L
and V
CC
, which set the logic
levels on the input and output sides of the translator. When
used to transfer data from the I/O V
L
to the I/O V
CC
ports,
input signals referenced to the V
L
supply are translated to
output signals with a logic level matched to V
CC
. In a
similar manner, the I/O V
CC
to I/O V
L
translation shifts
input signals with a logic level compatible to V
CC
to an
output signal matched to V
L
.
The NLSX5011 translator consists of bi−directional
channels that independently determine the direction of the
data flow without requiring a directional pin. One−shot
circuits are used to detect the rising or falling input signals.
In addition, the one−shots decrease the rise and fall times
of the output signal for high−to−low and low−to−high
transitions.
Input Driver Requirements
Auto−sense translators such as the NLSX5011 have a
wide bandwidth, but a relatively small DC output current
rating. The high bandwidth of the bi−directional I/O circuit
is used to quickly transform from an input to an output
driver and vice versa. The I/O ports have a modest DC
current output specification so that the output driver can be
over driven when data is sent in the opposite direction. For
proper operation, the input driver to the auto−sense
translator should be capable of driving 2 mA of peak output
current. The bi−directional configuration of the translator
results in both input stages being active for a very short time
period. Although the peak current from the input signal
circuit is relatively large, the average current is small and
consistent with a standard CMOS input stage.
Enable Input (EN)
The NLSX5011 translator has an Enable pin (EN) that
provides tri−state operation at the I/O pins. Driving the
Enable pin to a low logic level minimizes the power
consumption of the device and drives the I/O V
CC
and I/O
V
L
pins to a high impedance state. Normal translation
operation occurs when the EN pin is equal to a logic high
signal. The EN pin is referenced to the V
L
supply and has
Over−Voltage Tolerant (OVT) protection.
Uni−Directional versus Bi−Directional Translation
The NLSX5011 translator can function as a
non−inverting uni−directional translator. One advantage of
using the translator as a uni−directional device is that each
I/O pin can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
The values of the V
L
and V
CC
supplies can be set to
anywhere between 0.9 and 4.5 V. Design flexibility is
maximized because V
L
may be either greater than or less
than the V
CC
supply. In contrast, the majority of the
competitive auto sense translators has a restriction that the
value of the V
L
supply must be equal to less than (V
CC
0.4) V.
The sequencing of the power supplies will not damage
the device during power−up operation. In addition, the I/O
V
CC
and I/O V
L
pins are in the high impedance state if
either supply voltage is equal to 0 V. For optimal
performance, 0.01 to 0.1 mF decoupling capacitors should
be used on the V
L
and V
CC
power supply pins. Ceramic
capacitors are a good design choice to filter and bypass any
noise signals on the voltage lines to the ground plane of the
PCB. The noise immunity will be maximized by placing
the capacitors as close as possible to the supply and ground
pins, along with minimizing the PCB connection traces.
The NLSX5011 translators have a power down feature
that provides design flexibility. The output ports are
disabled when either power supply is off (V
L
or V
CC
= 0 V).
This feature causes all of the I/O pins to be in the power
saving high impedance state.
NLSX5011
www.onsemi.com
11
PACKAGE DIMENSIONS
UDFN6 1.2 x 1.0, 0.4P
CASE 517AA
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
E
D
BOTTOM VIEW
b
e
6X
0.10 B
0.05
AC
C
L5X
NOTE 3
2X
0.10 C
PIN ONE
REFERENCE
TOP VIEW
2X
0.10 C
10X
A
A1
(A3)
0.08 C
0.10 C
C
SEATING
PLANE
SIDE VIEW
L2
1
3
46
DIM MIN MAX
MILLIMETERS
A 0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b 0.15 0.25
D 1.20 BSC
E 1.00 BSC
e 0.40 BSC
L 0.30 0.40
L1 0.00 0.15
MOUNTING FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.22
6X
0.42
6X
1.07
0.40
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
L1
DETAIL A
Bottom View
(Optional)
A1
A3
DETAIL B
Side View
(Optional)
EDGE OF PACKAGE
MOLD CMPD
EXPOSED Cu
L2 0.40 0.50
NLSX5011
www.onsemi.com
12
PACKAGE DIMENSIONS
UDFN6 1.45x1.0, 0.5P
CASE 517AQ
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
A
B
E
D
BOTTOM VIEW
b
e
6X
0.10 B
0.05
AC
C
L6X
NOTE 3
0.10 C
PIN ONE
REFERENCE
TOP VIEW
0.10 C
6X
A
A1
0.05 C
0.05 C
C
SEATING
PLANE
SIDE VIEW
1
3
46
DIM MIN MAX
MILLIMETERS
A 0.45 0.55
A1 0.00 0.05
b 0.20 0.30
D 1.45 BSC
E 1.00 BSC
e 0.50 BSC
L 0.30 0.40
L1 −−− 0.15
DIMENSIONS: MILLIMETERS
0.30
6X
1.24
0.53
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.50
1
MOUNTING FOOTPRINT
PACKAGE
OUTLINE
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTIONS
A2 0.07 REF
6X
A2
DETAIL B
DETAIL A

NLSX5011MUTCG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels 1 BIT CONFIG TRANSLATOR
Lifecycle:
New from this manufacturer.
Delivery:
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