8
Switching Specications (AC)
-40°C ≤ T
A
≤ 100°C, 4.5V ≤ V
CC
≤ 20V, 6mA ≤ I
F(ON)
≤ 10 mA, 0V ≤ V
F(OFF)
≤ 0.8V.
All Typicals at T
A
= 25°C, I
F(ON)
= 6 mA unless otherwise specied.
Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time
to Logic Low Output
Leve
t
PHL
150 350 ns With Peaking Capacitor 5,6 5
Propagation Delay Time
to Logic High Output
Level
t
PLH
110 350 ns With Peaking Capacitor 5,6 5
Pulse Width Distortion PWD 250 ns | t
PHL
- t
PLH
| 8
Propagation Delay Dif-
ference Between Any 2
Parts
PDD -100 250 ns 10
Output Rise Time (10-
90%)
t
r
16 ns 5,8
Output Fall Time (90-
10%)
t
f
20 ns 5,8
Logic High Common
Mode Transient Immu-
nity
|CM
H
| -30000 V/µs |V
CM
| = 1000 V, I
F
= 6.0 mA,
V
CC
= 5 V, T
A
= 25 C
9 6
Logic Low Common
Mode Transient Immu-
nity
|CM
L
| 30000 V/µs |V
CM
| = 1000 V, V
F
= 0 V, V
CC
= 5 V, T
A
= 25 C
9 6
Package Characteristics
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level
safety specication or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.
Notes:
1. Derate total package power dissipation, P
T
, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
2. Duration of output short circuit time should not exceed 10 ms.
3. Input capacitance is measured between pin 2 and pin 3.
4. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
5. The t
PLH
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The t
PHL
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse.
6. C
MH
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V
O
> 2.0 V. C
ML
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V
O
< 0.8 V.
7. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second (leakage detec-
tion current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table, if applicable.
8. Pulse Width Distortion (PWD) is dened as |t
PHL
- t
PLH
| for any given device.
9. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 is recommended.
10. The dierence between t
PLH
and t
PHL
between any two devices under the same test condition.
Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage*
V
ISO
3750 V
rms
RH < 50%, t = 1 min.T
A
= 25°C
4,7
Input-Output Resistance R
I-O
10
12
W V
I-O
= 500 Vdc 4
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz, V
I-O
= 0 Vdc 4