74AHC_AHCT132_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 4 May 2009 6 of 17
NXP Semiconductors
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
10. Dynamic characteristics
C
O
output
capacitance
-4-----pF
74AHCT132
V
OH
HIGH-level
output voltage
V
I
= V
T+
or V
T
; V
CC
= 4.5 V
I
O
= 50 µA 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 8.0 mA 3.94 - - 3.80 - 3.70 - V
V
OL
LOW-level
output voltage
V
I
= V
T+
or V
T
; V
CC
= 4.5 V
I
O
=50µA - 0 0.1 - 0.1 - 0.1 V
I
O
= 8.0 mA - - 0.36 - 0.44 - 0.55 V
I
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
- - 0.1 - 1.0 - 2.0 µA
I
CC
supply current V
I
=V
CC
or GND; I
O
=0A;
V
CC
= 5.5 V
- - 2.0 - 20 - 40 µA
I
CC
additional
supply current
per input pin;
V
I
=V
CC
2.1 V; other pins
at V
CC
or GND; I
O
=0A;
V
CC
= 4.5 V to 5.5 V
- - 1.35 - 1.5 - 1.5 mA
C
I
input
capacitance
V
I
=V
CC
or GND - 3 10 - 10 - 10 pF
C
O
output
capacitance
-4-----pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C 40 °Cto+85°C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions 25 °C 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max Min Max
74AHC132
t
pd
propagation
delay
nA, nB to nY; see Figure 6
[2]
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF - 4.4 11.9 1.0 14.0 1.0 15.0 ns
C
L
= 50 pF - 6.2 15.4 1.0 17.5 1.0 19.5 ns
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF - 3.3 7.7 1.0 9.0 1.0 10.0 ns
C
L
= 50 pF - 4.7 9.7 1.0 11.0 1.0 12.5 ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
= GND to V
CC
[3]
-11- - - - -pF
74AHC_AHCT132_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 4 May 2009 7 of 17
NXP Semiconductors
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
[1] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
= 5.0 V).
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
11. Waveforms
74AHCT132; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
nA, nB to nY; see Figure 6
[2]
C
L
= 15 pF - 3.5 7.0 1.0 8.0 1.0 9.0 ns
C
L
= 50 pF - 5.0 8.0 1.0 9.0 1.0 10.0 ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
= GND to V
CC
[3]
-14- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions 25 °C 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
001aaa662
t
PHL
t
PLH
V
M
V
M
nA, nB input
nY output
GND
V
I
V
OH
V
OL
Table 8. Measurement points
Type Input Output
V
M
V
M
74AHC132 0.5 × V
CC
0.5 × V
CC
74AHCT132 1.5 V 0.5 × V
CC
74AHC_AHCT132_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 4 May 2009 8 of 17
NXP Semiconductors
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
Test data is given in Table 9.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= load capacitance including jig and probe capacitance.
Fig 7. Load circuitry for measuring switching times
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
Table 9. Test data
Type Input Load Test
V
I
t
r
, t
f
C
L
74AHC132 V
CC
3.0 ns 50 pF, 15 pF t
PLH
, t
PHL
74AHCT132 3.0 V 3.0 ns 50 pF, 15 pF t
PLH
, t
PHL

74AHC132BQ,115

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates QUAD 2-INPUT NAND
Lifecycle:
New from this manufacturer.
Delivery:
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