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MJD128T4G

P1-P3P4-P6
MJD128T4G (PNP)
www.onsemi.com
4
V
R
, REVERSE VOLTAGE (VOLTS)
C
ib
30
1 5 20 100
T
J
= 25°C
300
50
70
100
0.1 2 10 500.50.2
200
Figure 8. Capacitance
C, CAPACITANCE (pF)
C
ob
t, TIME OR PULSE WIDTH (ms)
1
0.01
100
0
0.3
0.2
0.07
r(t), EFFECTIVE TRANSIENT
R
q
JC(t)
= r(t) R
q
JC
R
q
JC
= 6.25°C/W
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
q
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.01
THERMAL RESISTANCE (NORMALIZED)
0.7
0.5
0.1
0.05
0.03
0.02
0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500
0.2
SINGLE PULSE
D = 0.5
0.05
0.1 0.5 30.3
0.2
0.7 1
5
I
C
, COLLECTOR CURRENT (AMP)
V
CC
= 30 V
I
C
/I
B
= 250
I
B1
= I
B2
T
J
= 25°C
t, TIME (s)μ
3
2
0.7
0.5
0.3
0.2
t
s
t
f
t
r
t
d
@ V
BE(off)
= 0 V
Figure 9. Switching Times Test Circuit Figure 10. Switching Times
0.1
1
10752
Figure 11. Thermal Response
V
2
A
PPROX
+8 V
0
≈ 8 k
SCOPE
V
CC
-30 V
R
C
51
FOR t
d
AND t
r
, D
1
IS DISCONNECTED
AND V
2
= 0
FOR
NPN
TEST
CIRCUIT
REVERSE
ALL
POLARITIES.
25 ms
t
r
, t
f
≤ 10 ns
DUTY CYCLE = 1%
+ 4 V
R
B
& R
C
VARIED TO OBTAIN DESIRED CURRENT LEVELS
D
1
, MUST BE FAST RECOVERY TYPE, e.g.:
1N5825 USED ABOVE I
B
≈ 100 mA
MSD6100 USED BELOW I
B
≈ 100 mA
V
1
A
PPROX
-12 V
TUT
R
B
D
1
≈ 120
0.07
0.05
0.1
0.01
MJD128T4G (PNP)
www.onsemi.com
5
I
C
, COLLECTOR CURRENT (AMP)
5
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
0.3
5
2
0.5
0.2
BONDING WIRE LIMIT
THERMAL LIMIT
T
C
= 25°C (SINGLE PULSE)
SECOND BREAKDOWN LIMIT
10 507
T
J
= 150°C
100ms
1ms
dc
0.1
1
3
15
20
3020 100
CURVES APPLY BELOW RATED V
CEO
5ms
Figure 12. Maximum Forward Bias
Safe Operating REA
321
10
0.05
0.02
0.03
500ms
120 200
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 12 is based on T
J(pk)
= 150°C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
< 150°C. T
J(pk)
may be calculated from the data in
Figure 11. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
Figure 13. Darlington Schematic
BASE
EMITTER
COLLECTOR
≈ 8 k ≈ 120
MJD128T4G (PNP)
www.onsemi.com
6
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
b
D
E
b3
L3
L4
b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
A 0.086 0.094 2.18 2.38
b 0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c 0.018 0.024 0.46 0.61
e 0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L 0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒ
mm
inches
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H 0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2
GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
e
BOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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MJD128/D
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P1-P3P4-P6

MJD128T4G

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Manufacturer:
ON Semiconductor
Description:
Darlington Transistors BIP PNP 8A 120V TR
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