NLV14490DWR2G

MC14490
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4
SWITCHING CHARACTERISTICS (Note 3) (C
L
= 50 pF, T
A
= 25_C)
Characteristic Symbol
V
DD
Vdc
Min
Typ
(Note 4)
Max Unit
Output Rise Time
All Outputs
t
TLH
5.0
10
15
180
90
65
360
180
130
ns
Output Fall Time Oscillator Output
Debounce Outputs
t
THL
5.0
10
15
100
50
40
200
100
80
ns
t
THL
5.0
10
15
60
30
20
120
60
40
Propagation Delay Time
Oscillator Input to Debounce Outputs
t
PHL
5.0
10
15
285
120
95
570
240
190
ns
t
PLH
5.0
10
15
370
160
120
740
320
240
Clock Frequency (50% Duly Cycle)
(External Clock)
f
cl
5.0
10
15
2.8
6
9
1.4
3.0
4.5
MHz
Setup Time (See Figure 1) t
su
5.0
10
15
100
80
60
50
40
30
ns
Maximum External Clock Input
Rise and Fall Time
Oscillator Input
t
r
, t
f
5.0
10
15
No Limit
ns
Oscillator Frequency
OSC
out
C
ext
100 pF*
Note: These equations are intended to be a design guide.
Laboratory experimentation may be required. Formulas are typically
± 15% of actual frequencies.
f
osc
, typ
5.0
10
15
1.5
C
ext
(in mF)
4.5
C
ext
(in mF)
6.5
C
ext
(in mF)
Hz
3. The formulas given are for the typical characteristics only at 25_C.
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
*POWERDOWN CONSIDERATIONS
Large values of C
ext
may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turnoff time of the power supply must not be faster than t = (V
DD
V
SS
) C
ext
/(10 mA). For example, If V
DD
V
SS
= 15
V and C
ext
= 1 mF, the power supply must turn off no faster than t = (15 V) (1 mF) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this
possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
Figure 1. Switching Waveforms Figure 2. Discharge Protection During Power Down
OSC
in
A
out
A
out
OSC
in
A
in
V
DD
0 V
V
DD
0 V
V
DD
0 V
50%
90%
50%
10%
t
r
t
f
t
PHL
90%
10%
50%
50%
t
su
50%
D1 D2C
ext
9
7
OSC
in
OSC
out
MC14490
t
PLH
V
DD
V
DD
MC14490
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5
THEORY OF OPERATION
The MC14490 Hex Contact Bounce Eliminator is
basically a digital integrator. The circuit can integrate both
up and down. This enables the circuit to eliminate bounce on
both the leading and trailing edges of the signal, shown in the
timing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
41/2bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in
Figure 4. The shift register requires a series of timing pulses
in order to shift the input signal into each shift register
location. These timing pulses (the clock signal) are
represented in the upper waveform of Figure 3. Each of the
six Bounce Eliminator circuits has an internal resistor as
shown in Figure 4. A pullup resistor was incorporated rather
than a pulldown resistor in order to implement switched
ground input signals, such as those coming from relay
contacts and push buttons. By switching ground, rather than
a power supply lead, system faults (such as shorts to ground
on the signal input leads) will not cause excessive currents
in the wiring and contacts. Signal lead shorts to ground are
much more probable than shorts to a power supply lead.
When the relay contact is closed, (see Figure 4) the low
level is inverted, and the shift register is loaded with a high
on each positive edge of the clock signal. To understand the
operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the positive edge of clock 1, the
input signal has bounced back to a high. This causes the shift
register to be reset to lows in all four bits — thus starting the
timing sequence over again.
During clock edges 3 to 6 the input signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 31/2 to 41/2 clock
period delay between the clean input signal and output
signal. In this example there is a delay of 3.8 clock periods
from the beginning of the clean input signal.
After some time period of N clock periods, the contact is
opened and at N + 1 a low is loaded into the first bit. Just after
N+1, when the input bounces low, all bits are set to a high.
At N+2 nothing happens because the input and output are
low and all bits of the shift register are high. At time N+3
and thereafter the input signal is a high, clean signal. At the
positive edge of N+6 the output goes high as a result of four
lows being shifted into the shift register.
Assuming the input signal is long enough to be clocked
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
The amount of time distortion between the input and
output signals is a function of the difference in bounce
characteristics on the edges of the input signal and the clock
frequency. Since most relay contacts have more bounce
when making as compared to breaking, the overall delay,
counting bounce period, will be greater on the leading edge
of the input signal than on the trailing edge. Thus, the output
signal will be shorter than the input signal — if the leading
edge bounce is included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state.
Referring to Figure 3, a false state is seen to occur three times
at the beginning of the input signal. The input signal goes
low three times before it finally settles down to a valid low
state. The first three low pulses are referred to as false states.
If the user has an available clock signal of the proper
frequency, it may be used by connecting it to the oscillator
input (pin 7). However, if an external clock is not available
the user can place a small capacitor across the oscillator
input and output pins in order to start up an internal clock
source (as shown in Figure 4). The clock signal at the
oscillator output pin may then be used to clock other
MC14490 Bounce Eliminator packages. With the use of the
MC14490, a large number of signals can be cleaned up, with
the requirement of only one small capacitor external to the
Hex Bounce Eliminator packages.
Figure 3. Timing Diagram
OSC
in
OR OSC
out
INPUT
OUTPUT
CONTACT
OPEN
CONTACT
BOUNCING
CONTACT CLOSED
(VALID TRUE SIGNAL)
CONTACT
BOUNCING
CONTACT OPEN
N + 7N + 5N + 3N + 1654321
MC14490
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6
Figure 4. Typical “Form A” Contact Debounce Circuit
(Only One Debouncer Shown)
1/2 BIT
DELAY
OSCILLATOR
AND
TWO-PHASE
CLOCK GENERATOR
C
ext
OSC
out
OSC
in
“FORM A”
CONTACT
A
in
1
9
7
φ 1
φ 2
DATA
SHIFT LOAD
4-BIT STATIC SHIFT REGISTER
φ 1 φ 2
φ 1 φ 2
15
A
out
+V
DD
PULLUP RESISTOR
(INTERNAL)
OPERATING CHARACTERISTICS
The single most important characteristic of the MC14490
is that it works with a single signal lead as an input, making
it directly compatible with mechanical contacts (Form A
and B).
The circuit has a builtin pullup resistor on each input.
The worst case value of the pullup resistor (determined from
the Electrical Characteristics table) is used to calculate the
contact wetting current. If more contact current is required,
an external resistor may be connected between V
DD
and the
input.
Because of the builtin pullup resistors, the inputs cannot
be driven with a single standard CMOS gate when V
DD
is
below 5 V. At this voltage, the input should be driven with
paralleled standard gates or by the MC14049 or MC14050
buffers.
The clock input circuit (pin 7) has Schmitt trigger shaping
such that proper clocking will occur even with very slow
clock edges, eliminating any need for clock preshaping. In
addition, other MC14490 oscillator inputs can be driven
from a single oscillator output buffered by an MC14050 (see
Figure 5). Up to six MC14490s may be driven by a single
buffer.
The MC14490 is TTL compatible on both the inputs and
the outputs. When V
DD
is at 4.5 V, the buffered outputs can
sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as
a result of the internal input pullup resistors.
Figure 5. Typical Single Oscillator Debounce System
FROM CONTACTS MC14490
TO SYSTEM
LOGIC
OSC
in
OSC
out
C
ext
1/6 MC14050
97
OSC
in
7 9OSC
out
NO CONNECTION
FROM
CONTACTS
TO SYSTEM
LOGIC
MC14490
NO CONNECTION
9OSC
out
OSC
in
7
FROM CONTACTS MC14490
TO SYSTEM
LOGIC

NLV14490DWR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Specialty Function Logic HEX BOUNCE ELIMINATOR
Lifecycle:
New from this manufacturer.
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