6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
5
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5. For the examples shown here, BEn may correspond to any of the eight byte enable signals.
Truth Table I—Read/Write and Enable Control
(1,2,3,4,5)
OE
CLK
CE
0
CE
1
Byte Enables R/W ZZ I/O Operation
(6)
MODE
X
H X All BE = X X
L
All Bytes= High-Z Deselected: Power Down
X
X L All BE = X X
L
All Bytes = High-Z Deselected: Power Down
X
L H All BE = H X
L
All Bytes = High-Z All Bytes Deselected
X
LH
BE
n
= L,
All other
BE
= H
L
L
Byte
n
= D
IN
,
All other
Bytes
= High-Z Write to Byte X Only
X
LH
BE
4-7
= L,
BE
0-3
= H
L
L
Byte
4-7
= D
IN
,
Byte
0-3
= High-Z Write to Lower Bytes Only
X
LH
BE
4-7
= H, BE
0-3
= L
L
L
Byte
4-7
= High-Z, Byte
0-3
= D
IN
Write to Upper Bytes Only
X
LH
BE
0-7
= L
L L Byte
0-7
= D
IN
Write to All Bytes
L
LH
BE
n
= L,
All other
BE
= H
H
L
Byte
n
= D
OUT
,
All other
Bytes
= High-Z Read Byte X Only
L
LH
BE
4-7
= L,
BE
0-3
= H
HLByte
4-7
= D
OUT
,
Byte
0-3
= High-Z Read Lower Bytes Only
L
LH
BE
4-7
= H, BE
0-3
= L
HLByte
4-7
= High-Z, Byte
0-3
= D
OUT
Read Upper Bytes Only
L
LHAll BE = L H L All Bytes = D
OUT
Read All Bytes
HXXXAll BE = X X L All Bytes =
High-Z Outputs Disabled
XXXXAll BE =
X X H All Bytes =
High-Z Sleep Mode
5687 tbl 03
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
0, CE1 and BEn.
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
Address
Previous
Internal
Address
Internal
Address
Used CLK
ADS
(4)
CNTEN REPEAT
(4,6)
I/O
(3)
MODE
An X An
LX
HD
I/O
(n)
External Address Used
XAnAn + 1
H L
(5)
HD
I/O
(n+1)
Counter Enabled-Internal Address generation
X An + 1 An + 1
HH
HD
I/O
(n+1)
Enabled Address Blocked-Counter disabled (An + 1 reused)
XXAn
X X
LD
I/O
(n)
Counter Set to last valid ADS load
5687 tbl 04
