14
Dead Time and Propagation Delay Specications
The HCPL-3020 and HCPL-0302 include a Propagation
Delay Dierence (PDD) specication intended to help
designers minimize “dead time” in their power inverter
designs. Dead time is the time high and low side power
transistors are o. Any overlap in Ql and Q2 conduction
will result in large currents owing through the power
devices from the high voltage to the low-voltage motor
rails. To minimize dead time in a given design, the turn
on of LED2 should be delayed (relative to the turn o of
LED1) so that under worst-case conditions, transistor Q1
has just turned o when transistor Q2 turns on, as shown
in Figure 24. The amount of delay necessary to achieve
this condition is equal to the maximum value of the propa-
gation delay dierence specication, PDD max, which is
specied to be 500 ns over the operating temperature
range of –40° to 100°C.
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the dierence between the maximum and minimum
propagation delay dierence specication as shown in
Figure 25. The maximum dead time for the HCPL-3020 and
HCPL-0302 is 1 ms (= 0.5 µs – (–0.5 µs)) over the operating
temperature range of –40°C to 100°C.
CMR with the LED On (CMR
H
)
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving
the LED current beyond the input threshold so that it is not
pulled below the threshold during a transient. A minimum
LED current of 7 mA provides adequate margin over the
maximum I
FLH
of 6 mA to achieve 10 kV/µs CMR.
CMR with the LED O (CMR
L
)
A high CMR LED drive circuit must keep the LED o (V
F
V
F(OFF)
) during common mode transients. For example,
during a -dV
CM
/dt transient in Figure 21, the current ow-
ing through C
LEDP
also ows through the R
SAT
and V
SAT
of
the logic gate. As long as the low state voltage developed
across the logic gate is less than V
F(OFF)
the LED will remain
o and no common mode failure will occur.
The open collector drive circuit, shown in Figure 22, cannot
keep the LED o during a +dV
CM
/dt transient, since all the
current owing through C
LEDN
must be supplied by the
LED, and it is not recommended for applications requiring
ultra high CMR
1
performance. The alternative drive circuit,
which likes the recommended application circuit (Figure
17), does achieve ultra high CMR performance by shunting
the LED in the o state.
Note that the propagation delays used to calculate PDD and dead time are
taken at equal temperatures and test conditions since the optocouplers
under consideration are typically mounted in close proximity to each
other and are switching identical IGBTs.
