MC74HC377ADTR2G

© Semiconductor Components Industries, LLC, 2010
February, 2010 Rev. 1
1 Publication Order Number:
MC74HC377A/D
MC74HC377A
Octal D Flip-Flop with
Common Clock and Enable
HighPerformance SiliconGate CMOS
The MC74HC377A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flipflops with common Clock and
Enable (E) inputs. Each flipflop is loaded with a lowtohigh
transition of the Clock input. Enable (E) is active low.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 264 FETs or 66 Equivalent Gates
These are PbFree Devices
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1
20
MARKING
DIAGRAMS
SOIC20
DW SUFFIX
CASE 751D
HC377A
AWLYYWWG
HC
377A
ALYWG
G
TSSOP20
DT SUFFIX
CASE 948E
1
1
20
1
20
20
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = PbFree Package
G = PbFree Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
Q2
D1
D0
Q0
E
GND
Q3
D3
D2
Q1 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
CLOCK
Q4
D4
D5
Q5
MC74HC377A
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2
Figure 1. Logic Diagram
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
E
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
FUNCTION TABLE
Operating
Modes
Inputs Outputs
Clock E Dn Qn
Load “1” l h H
Load “0” l l L
Hold (Do Nothing)
X
h
H
X
X
No Change
No Change
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOWto
HIGH CP transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the LOWtoHIGH
CP transition
= LOWtoHIGH CP transition
X = Don’t Care
Design Criteria Value Units
Internal Gate Count* 66 ea
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product .0075 pJ
*Equivalent to a twoinput NAND gate.
ORDERING INFORMATION
Device Package Shipping
MC74HC377ADWG SOIC20 WIDE
(PbFree)
38 Units / Rail
MC74HC377ADWR2G SOIC20 WIDE
(PbFree)
1000 Tape & Reel
MC74HC377ADTG TSSOP20* 75 Units / Rail
MC74HC377ADTR2G TSSOP20* 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
MC74HC377A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air SOIC Package
TSSOP Package
500
450
mW
T
stg
Storage Temperature –65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 2) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74HC377ADTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops D-Type Flip-Flop 6V 1.5ns 2V
Lifecycle:
New from this manufacturer.
Delivery:
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