MPQ18021A―100V, 2.5A, HIGH-FREQUENCY HALF-BRIDGE GATE DRIVER
MPQ18021A Rev. 1.0 www.MonolithicPower.com 4
12/10/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS (continued)
VDD = V
BST
-V
SW
=12V, VSS=V
SW
= 0V, No load at DRVH and DRVL, T
J
= -40°C to +125°C, Typical
Value are T
J
=25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Switching Spec. --- Low Side Gate Driver
Turn-off propagation delay
INL falling to DRVL falling
T
DLFF
16 ns
Turn-on propagation delay
INL rising to DRVL rising
T
DLRR
16
DRVL rise time C
L
=1nF 12 ns
DRVL fall time C
L
=1nF 9 ns
Switching Spec. --- Floating Gate Driver
Turn-off propagation delay
INL falling to DRVH falling
T
DHFF
16 ns
Turn-on propagation delay
INL rising to DRVH rising
T
DHRR
16 ns
DRVH rise time C
L
=1nF 12 ns
DRVH fall time C
L
=1nF 9 ns
Switching Spec. --- Matching
Floating driver turn-off to low
side driver turn-on
T
MON
1 5 ns
Low side driver turn-off to floating
driver turn-on
T
MOFF
1 5 ns
Minimum input pulse width that
changes the output
T
PW
50
(5)
ns
Bootstrap diode turn-on or turn-
off time
T
BS
10
(5)
ns
Note:
5) Guaranteed by design.
INPUT
(INH, INL)
OUTPUT
(DRVH,
DRVL)
T
DHRR
, T
DLRR
T
DHFF
, T
DLFF
INPUT
(INH, INL)
OUTPUT
(DRVH,
DRVL)
T
DHRR
, T
DLRR
T
DHFF
, T
DLFF
INL
INH
DRVL
DRVH
T
MON
T
MOFF
Figure 1: Timing Diagram
