QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1185
DUAL PHASE/DUAL OUTPUT SYNCHRONOUS BUCK CONVERTER
2
QUICK START PROCEDURE
Demonstration circuit 1185 is easy to set up to evaluate
the performance of the LTC3850EUF. Refer to Figure 1
for the proper measurement equipment setup and follow
the procedure below:
NOTE:
When measuring the output or input voltage rip-
ple, care must be taken to avoid a long ground lead on
the oscilloscope probe. See Figure 2 for the proper
scope probe technique. Short, stiff leads need to be sol-
dered to the (+) and (-) terminals of an output capacitor.
The probe’s ground ring needs to touch the (-) lead and
the probe tip needs to touch the (+) lead.
Place jumpers in the following positions:
JP1 RUN1 ON
JP2 RUN2 ON
JP3 MODE CCM
With power off, connect the input power supply to VIN
and GND.
Turn on the power at the input.
NOTE:
Make sure that the input voltage does not exceed
15V.
Check for the proper output voltages.
Version –A:
Vout1 = 1.960V to 2.040V
Vout2 = 1.764V to 1.836V
Version –B:
Vout1 = 1.470V to 1.530V
Vout2 = 1.176V to 1.224V
Once the proper output voltages are established, adjust
the loads within the operating range and observe the
output voltage regulation, ripple voltage, efficiency and
other parameters.
NOTE:
Do not apply load across the VOSn+ and VOSn-
turrets. These turrets are only intended to Kelvin sense
the output voltage across COUT1 and COUT4. Heavy
load currents may damage the output voltage sense
traces.
SINGLE OUTPUT / DUAL PHASE OPERATION
A single output / dual phase converter may be preferred
for high output current applications. The benefits of sin-
gle output / dual phase operation is lower ripple current
through the input and output capacitors, improved load
step response and simplified thermal design. To imple-
ment single output / dual phase operation, make the fol-
lowing modifications:
1.
Tie VOUT1 to VOUT2 by tying together the ex-
posed copper pads near J3 and J5 at the edge of
the board. Use a piece of heavy copper foil.
2. Tie ITH1 to ITH2 by stuffing 0
Ω
at R49.
3. Tie VFB1 to VFB2 by stuffing 0
Ω
at R50.
4. Tie TRK/SS1 to TRK/SS2 by stuffing 0
Ω
at
R52.
5. Tie RUN1 to RUN2 by stuffing 0
Ω
at R55.
6.
Remove the redundant ITH compensation
network and VFB divider.