13
640220fa
LT6402-20
APPLICATIO S I FOR ATIO
WUU
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solution of 14pF from each fi ltered output to ground plus
a 14pF capacitor between the fi ltered outputs would also
halve the fi lter bandwidth (Figure 7).
Bandpass fi ltering is also easily implemented with just a
few external components. An additional 560pF and 62nH,
each added differentially between +OUTFILTERED and
–OUTFILTERED creates a bandpass fi lter with a 26MHz
center frequency, –3dB points of 23MHz and 30MHz, and
1.6dB of insertion loss (Figure 8).
Output Common Mode Adjustment
The LT6402-20’s output common mode voltage is set by
the V
OCM
pin. It is a high-impedance input, capable of
setting the output common mode voltage anywhere in
a range from 1.1V to 3.6V. Bandwidth of the V
OCM
pin is
typically 200MHz, so for applications where the V
OCM
pin
is tied to a DC bias voltage, a 0.1µF capacitor at this pin is
recommended. For best distortion performance, the voltage
at the V
OCM
pin should be between 1.8V and 2.6V.
When interfacing with most ADCs, there is generally a
V
OCM
output pin that is at about half of the supply voltage
of the ADC. For 5V ADCs such as the LTC17XX family, this
V
OCM
output pin should be connected directly (with the
addition of a 0.1µF capacitor) to the input V
OCM
pin of the
LT6402-20. For 3V ADCs such as the LTC22XX families,
the LT6402-20 will function properly using the 1.65V from
the ADC’s V
CM
reference pin, but improved Spurious Free
Dynamic Range (SFDR) and distortion performance can
be achieved by level-shifting the LTC22XX’s V
CM
reference
voltage up to at least 1.8V. This can be accomplished as
shown in Figure 9 by using a resistor divider between the
LTC22XX’s V
CM
output pin and V
CC
and then bypassing
the LT6402-20’s V
OCM
pin with a 0.1µF capacitor. For a
common mode voltage above 1.9V, AC coupling capacitors
are recommended between the LT6402-20 and LTC22XX
ADCs because of the input voltage range constraints of
the ADC.
Large Output Voltage Swings
The LT6402-20 has been designed to provide the
3.2V
P-P
output swing needed by the LTC1748 family
of 14-bit low-noise ADCs. This additional output swing
improves system SNR by up to 4dB.
Input Bias Voltage and Bias Current
The input pins of the LT6402-20 are internally biased to
the voltage applied to the V
OCM
pin. No external biasing
resistors are needed, even for AC-coupled operation. The
input bias current is determined by the voltage difference
between the input common mode voltage and the V
OCM
pin (which sets the output common mode voltage). For
example, if the inputs are tied to 2.5V with the V
OCM
pin
at 2.2V, then a total input bias current of 1mA will fl ow
into the LT6402-20’s +INA and +INB pins. Furthermore,
an additional input bias current totaling 1mA will fl ow into
the –INA and –INB inputs.
Application (Demo) Boards
The DC954A Demo Board has been created for stand-alone
evaluation of the LT6402-20 with either single-ended or
differential input and output signals. As shown, it accepts
a single-ended input and produces a single-ended output
so that the LT6402-20 can be evaluated using standard
laboratory test equipment. For more information on this
Demo Board, please refer to the layout and schematic
diagrams found later in this data sheet.
There are also additional demo boards available that
combine the LT6402-20 with a variety of different Linear
Technology ADCs. Please contact the factory for more
information on these demo boards.
6402 F9
IF IN
LT6402-20
–INA
–INB
V
OCM
2
31
6
7
1
2
+INB
+INA
14
13
15
121Ω
16
10Ω
10Ω
LTC22xx
0.1µF
0.1µF
+OUTFILTERED
–OUTFILTERED
AIN
+
AIN
–
4.02k
11k
1.9V
1.5V
3V
V
CM
Figure 9. Level Shifting 3V ADC V
CM
Voltage for
Improved SFDR
