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TLE6232GPAUMA2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Data Sheet TLE 6232 GP
V2.3 Page 2009-11-18
7
Description of the Power Stages
4 low side power switches for nominal currents up to 3A (power stages OUT1 to OUT4). Con-
trol is possible by input pins or via SPI. For T
J
= 150°C the on-resistance of the power
switches is below 500mΩ.
2 low side power switches for nominal currents up to 1.5A (power stages OUT5 and OUT6).
Control is possible by input pins or via SPI. For T
J
= 150°C the on-resistance of the power
switches is below 1Ω.
In order to increase the switching current or to reduce the power dissipation parallel connec-
tion of power stages is possible.
Each of the 6 output stages is equipped with its own zener clamp, which limits the output volt-
age to a maximum of 60V. The outputs are provided with a current limitation set to a minimum
of 1.5A resp. 3A. Each power stage is equipped with an own temperature sensor.
Each output is protected by embedded protection functions
5)
. In case of overload or short-
circuit to U
Batt
the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an over-temperature condition, a second protection
level (about 170°C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
The following faults can be detected (individually for each output):
- short to UBatt: (SCB/overload) can be detected when switches are On state
- short to ground: (SCG) can be detected when switches are Off state
- open load: (OL) can be detected when switches are Off state
- over-temperature: (OT) will only be detected when switches are On state
The fault conditions SCB, SCG and OL will not be stored until an integrated filtering time is
expired (please note for PWM application). If, at one output, several errors occur in a se-
quence, always the last detected error will be stored (with filtering time). All fault conditions
are encoded in two bits per switch and are stored in the corresponding SPI registers. Additio-
nally there are two central diagnostic bits: one especially for over-temperature (latched result
of an OR-operation out of the 6 signals of the temperature sensor) and one for fault occur-
rence at any output. A fault that has been detected and stored in the fault register must not be
replaced by o.k.-state (11) unless it is read out by the RD_DIAG command sent by the micro-
controller or an internal or external reset has been applied. I.e. the fault register will be
cleared only by the RD_DIAG command.
PRG - Program pin. PRG = High (V
S
): Parallel inputs Channel 1 to 6 are high active
PRG = Low (GND): Parallel inputs Channel 1 to 6 are low active.
If the parallel input pins are not connected (independent of high or low activity), channels 1 to
6 are switched OFF.
PRG pin itself is internally pulled down when it is not connected.
5)
The integrated protection functions prevent device destruction under fault conditions and may not be used in
normal operation or permanently.
Data Sheet TLE 6232 GP
V2.3 Page 2009-11-18
8
The effect of the integrated under-voltage detection is similar to the effect of an external reset
at pin Reset (except low current consumption):
- locks all power switches regardless of their input signals
- clears the fault registers
- resets SPI control register
Parallel Connection of Power Stages
The power stages which are connected in parallel have to be switched on and off simultane-
ously.
In case of overload the ground current and the power dissipation are increasing. The applica-
tion has to take into account that all maximum ratings are observed (e.g. operating tempera-
ture T
J
and total ground current I
GND
, see Maximal Ratings).
The maximum current limitation value (or overload detection threshold) of the parallel con-
nected power stages is the summation of the corresponding maximum values of the power
stages (IOUT
(lim)x
+ I
OUT(lim)y
+ ....).
Max. Nominal Current Max. Clamping Energy
On Resistance
2 power stages of the
same type
(see note 1)
(I
max,OUTx
+I
max,OUTy
) x 0.9
0.8 x (Ex + Ey)
yOUTxON
xR
,,
5.0
3 power stages of the
same type
(see note 1,2)
(I
max,OUTx
+I
max,OUTy
+
I
max,OUTz
) x 0.8
0.7 x (Ex + Ey + Ez)
zyOUTxON
xR
,,,
34.0
2 power stages with the
same clamping voltage,
but different nominal
current (see note 3)
(I
max,OUTx
+I
max,OUTy
) x 0.8
Min (Eclpx , Eclpy)
OUTyONOUTxON
OUTyONOUTxON
RR
xRR
,,
,,
+
Note 1: Power stages of the same type have the same nominal current
Note 2: Only for 3A power stages
Note 3: Parallel connection of power stage type 3A/53V with type 1.5A/53V
SPI Interface
The serial SPI interface makes possible communication between TLE6232 and the microcon-
troller.
TLE 6232 GP always works in slave mode whereas the microcontroller provides the master
function. The maximum baud rate is 5MBaud.
Applying a chip select signal at CS and setting bit 7 and bit 6 of the instruction byte to „1“ and
„0“ TLE 6232 GP is selected by the SPI master. SI is the data input (Signal In), SO the data
output
(Signal Out). Via SCLK (Serial Clock Input) the SPI clock is given by the master.
Data Sheet TLE 6232 GP
V2.3 Page 2009-11-18
9
SPI Signal Description
CS
- Chip Select. The system microcontroller selects the TLE 6232 GP by means of the
CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS
High to Low transition: - diagnostic status information is transferred from the power
outputs into the shift register.
- serial input data can be clocked in from then on
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits
CS
Low to High transition: - transfer of SI bits from shift register into output buffers
- reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of
CS
. When
CS
is in a logic high state, any signals at the SCLK and
SI pins are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6232 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select
CS
makes any transition. The number of clock pulses will be counted during a
chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were
counted during
CS
is active.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-
mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of two bytes - a "control byte” followed by a "data byte". The control
byte contains the information as to whether the data byte will be accepted or ignored (see di-
agnostics section). The data byte contains the input information for the six channels. A logic
high level at this pin (within the data byte) will switch on the power switch, provided that the
corresponding parallel input is also switched on (AND-operation for channel 1 to 6).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the
CS
pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET
- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
In case of inactive chip select signal (High) or bit 7 and bit 6 of the instruction byte differing
from1“ and „0“ the data output SO remains into tri-state.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

TLE6232GPAUMA2

Mfr. #:
Buy TLE6232GPAUMA2
Manufacturer:
Infineon Technologies
Description:
Power Switch ICs - Power Distribution SMART 6 CHANNEL LW-SIDE SWITCH
Lifecycle:
New from this manufacturer.
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