ACPL-M75L-500E

7
Application Information
Bypassing and PC Board Layout
The ACPL-M75L optocoupler is extremely easy to use.
ACPL-M75L provides CMOS logic output due to the high-
speed CMOS IC technology used.
The external components required for proper operation
are the input limiting resistor and the output bypass ca-
pacitor. Capacitor values should be between 0.01 µF and
0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm.
Figure 8. Recommended printed circuit board layout
Figure 7. Typical V
F
vs. temperature.
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation delay is a gure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low to high (t
PLH
) is the amount
of time required for an input signal to propagate to the
output, causing the output to change from low to high.
Similarly, the propagation delay from high to low (t
PHL
) is
the amount of time required for the input signal to propa-
gate to the output, causing the output to change from
high to low (see Figure 9).
Figure 9. Propagation delay and skew waveform
Figure 10. Parallel data transmission example
t
PSK
t
PSK
50%
50%
t
PSK
I
F
V
O
I
F
V
O
2.5 V,
CMOS
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
-
40 -20 0 20 40 60 80 100
T
A
- TEMPERATURE -
o
C
V
F
- FORWARD VOLTAGE - C
5
4
3
1
2
I
in
V
DD2
V
O
Gnd2
XXX
YWW
C
C = 0.01 uF to 0.1uF
Gnd1
8
Pulse-width distortion (PWD) results when t
PLH
and t
PHL
dier in value. PWD is dened as the dierence between
t
PLH
and t
PHL
and often PWD determines the maximum
data rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse width
is tolerable; the exact gure depends on the particular ap-
plication (RS232, RS422, T-1, etc.).
Propagation delay skew, t
PSK
, is an important parameter
to consider in parallel data applications where synchroni-
zation of signals on parallel data lines is a concern.
If the parallel data is being sent through a group of opto-
couplers, dierences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at dier-
ent times. If this dierence in propagation delays is large
enough, it will determine the maximum rate at which par-
allel data can be sent through the optocouplers.
Propagation delay skew is dened as the dierence be-
tween the minimum and maximum propagation delays,
either t
PLH
or t
PHL
, for any given group of optocouplers
which are operating under the same conditions (i.e., the
same supply voltage, output load, and operating temper-
ature). As illustrated in Figure 10, if the inputs of a group of
optocouplers are switched either ON or OFF at the same
time, t
PSK
is the dierence between the shortest propaga-
tion delay, either t
PLH
or t
PHL
, and the longest propagation
delay, either t
PLH
or t
PHL
. As mentioned earlier, t
PSK
can de-
termine the maximum parallel data transmission rate.
Figure 10 is the timing diagram of a typical parallel data
application with both the clock and the data lines being
sent through optocouplers. The gure shows data and
clock signals at the inputs and outputs of the optocou-
plers. To obtain the maximum data transmission rate, both
edges of the clock signal are being used to clock the data;
if only one edge were used, the clock signal would need
to be twice as fast.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an opt-
ocoupler. Figure 10 shows that there will be uncertainty in
both the data and the clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived.
From these considerations, the absolute minimum pulse
width that can be sent through optocouplers in a parallel
application is twice t
PSK
. A cautious design should use a
slightly longer pulse width to ensure that any additional
uncertainty in the rest of the circuit does not cause a
problem.
The t
PSK
specied optocouplers oer the advantages of
guaranteed specications for propagation delays, pulse-
width distortion and propagation delay skew over the rec-
ommended temperature, and power supply ranges.
Figure 11. Connection of peaking capacitor (Cpeak) in parallel of the input
limiting resistor (Rlimit) to improve speed performance
Figure 12. Improvement of tp and PWD with added 100pF peaking capacitor in parallel of input limiting resistor.
0
5
10
15
20
25
30
35
-40 -20 0 20 40 60 80 100
t
PHL
t
PLH
t
PLH
t
PHL
|PWD|
Without peaking cap
0
5
10
15
20
25
30
35
40
-40 -20 0 20 40 60 80 100
t
PHL
t
PLH
t
PHL
t
PLH
|PWD|
With peaking cap
Without peaking cap
(ii) V
DD
=3.3V, C
peak
=100pF, R
limit
=250Ω
(i) V
DD
=5V, C
peak
=100pF, R
limit
=530Ω
GND
2
V
DD2
0.1 µF
GND
1
R
limit
SHIEL
V
in
+
-
C
peak
V
O
R
drv
= 50
SHIELD
+
-
9
Table 1. Eects of Common Mode Pulse Direction on Transient I
LED
If dV
CM
/dt Is: then I
LP
Flows: and I
LN
Flows:
If |I
LP
| < |I
LN
|,
LED I
F
Current
Is Momentarily:
If |I
LP
| > |I
LN
|,
LED I
F
Current
Is Momentarily:
positive (>0) away from LED
anode through C
LA
away from LED
cathode through C
LC
increased decreased
negative (<0) toward LED
anode through C
LA
toward LED
cathode through C
LC
decreased increased
Powering Sequence
V
DD
needs to achieve a minimum level of 3V before pow-
ering up the output connecting component.
Input Limiting Resistors
ACPL-M75L is direct current driven (Figure 8), and thus
eliminate the need for input power supply. To limit the
amount of current owing through the LED, it is recom-
mended that a 530ohm resistor is connected in series with
anode of LED (i.e. Pin 1 for ACPL-M75L) at 5V input signal.
At 3.3V input signal, it is recommended to connect 250Ω
resistor in series with anode of LED. The recommended
limiting resistors is based on the assumption that the driv-
er output impedence is 50Ω (as shown in Figure 11).
Speed Improvement
A peaking capacitor can be placed across the input cur-
rent limit resistor (Figure 11) to achieve enhanced speed
performance. The value of the peaking cap is dependent
to the rise and fall time of the input signal and supply volt-
ages and LED input driving current (I
f
). Figure 12 shows
signicant improvement of propagation delay and pulse
with distortion with added peak capacitor at driving cur-
rent of 6mA for both 3.3V and 5V power supply.
Common Mode Rejection for ACPL-M75L
Figure 13 shows the recommended drive circuit for the
ACPL-M75L for optimal common-mode rejection perfor-
mance. Two LED-current setting resistors are used instead
of one. This is to balance the common mode impedance
at LED anode and cathode. Common-mode transients can
capacitively couple from the LED anode (or cathode) to
the output-side ground causing current to be shunted
away from the LED (which can be bad if the LED is on) or
conversely cause current to be injected into the LED (bad
if the LED is meant to be o). Figure14 shows the parasitic
capacitances which exists between LED anode/cathode
and output ground (C
LA
and C
LC
). Also shown in Figure 14
on the input side is an AC-equivalent circuit.
Table 1 indicates the directions of I
LP
and I
LN
ow depend-
ing on the direction of the common-mode transient. For
transients occurring when the LED is on, common-mode
rejection (CM
L
, since the output is in the “low state) de-
pends upon the amount of LED current drive (I
F
). For con-
ditions where I
F
is close to the switching threshold (I
TH
),
CM
L
also depends on the extent which I
LP
and I
LN
balance
each other. In other words, any condition where common-
mode transients cause a momentary decrease in I
F
(i.e.
when dV
CM
/dt>0 and |I
FP
| > |I
FN
|, referring to Table 1) will
cause common-mode failure for transients which are fast
enough.
Likewise for common-mode transients which occur when
the LED is o (i.e. CM
H
, since the output is “high”), if an im-
balance between I
LP
and I
LN
results in a transient I
F
equal
to or greater than the switching threshold of the optocou-
pler, the transient signal” may cause the output to spike
below 2V (which constitutes a CM
H
failure).
By using the recommended circuit in Figure 13, good CMR
can be achieved. The resistors recommended in Figure 13
include both the output impedence of the logic driver cir-
cuit and the external limiting resistor. The balanced I
LED
-
setting resistors help equalize the common mode voltage
change at anode and cathode to reduce the amount by
which I
LED
is modulated from transient coupling through
C
LA
and C
LC
.

ACPL-M75L-500E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 15MBd 10k V/us
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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