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8344BYILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Low Skew, 1-to-24 Differential-to-
LVCMOS/LVTTL Fanout Buffer
8344I
Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20151
GENERAL DESCRIPTION
The 8344I is a low voltage, low skew fanout buffer and a member
of the family of High Performance Clock Solutions from IDT. The
8344I has two selectable clock inputs. The CLK0, nCLK0 and CLK1,
nCLK1 pairs can accept most standard differential input levels.
The 8344I is designed to translate any differential signal levels
to LVCMOS/LVTTL levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to 48
by utilizing the ability of the outputs to drive two series terminated
lines. Redundant clock applications can make use of the dual clock
input. The dual clock inputs also facilitate board level testing. 8344I
is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V
output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
8344I ideal for those clock distribution applications demanding well
defi ned performance and repeatability.
FEATURES
• Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
• Two selectable differential clock input pairs for redundant
clock applications
• CLKx, nCLKx pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 100MHz
• Translates any single-ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
• Multiple output enable pins for disabling unused outputs
in reduced fanout applications
• Output skew: 275ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 150ps (maximum)
• Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
OE1
OE2
OE3
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
V
DD
GND
CLK_SEL
Q8
Q9
V
DDO
GND
Q10
Q11
Q12
Q13
V
DDO
GND
Q14
Q15
48-Lead LQFP
7mm x 7mm x 1.4mm pack-
age body
Y Package
Top View
8344I
8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20152
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Output
Single-ended LVCMOS/LVTTL outputs.
7Ω typical output impedance.
3, 9, 28,
34, 39, 45
V
DDO
Power Output supply pins.
4, 10, 14,18,
27, 33, 40, 46
GND Power Power supply ground.
13 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
When LOW, selects CLK0, nCLK0.
LVTTL / LVCMOS interface levels.
15, 19 V
DD
Power Positive supply pins.
16 nCLK1 Input Pullup Inverting differential clock input.
17 CLK1 Input Pulldown Non-inverting differential clock input.
20 nCLK0 Input Pullup Inverting differential clock input.
21 CLK0 Input Pulldown Non-inverting differential clock input.
22 OE3 Input Pullup
Output enable. Controls enabling and disabling of outputs
Q16 through Q23. LVCMOS/LVTTL interface levels.
23 OE2 Input Pullup
Output enable. Controls enabling and disabling of outputs
Q8 through Q15. LVCMOS/LVTTL interface levels.
24 OE1 Input Pullup
Output enable. Controls enabling and disabling of outputs
Q0 through Q7. LVCMOS/LVTTL interface levels.
25, 26, 29, 30
31, 32, 35, 36
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Output
Single-ended LVCMOS/LVTTL outputs.
7Ω typical output impedance.
37, 38, 41, 42
43, 44, 47, 48
Q8, Q9, Q10, Q11
Q12, Q13, Q14, Q15
Output
Single-ended LVCMOS/LVTTL outputs.
7Ω typical output impedance.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance
(per output)
20 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
R
OUT
Output Impedance 7
Ω
8344I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20153
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. CLOCK SELECT FUNCTION TABLE
TABLE 3C. CLOCK INPUTS FUNCTION TABLE
Bank 1 Bank 2 Bank 3
Input Output Input Output Input Output
OE1 Q0-Q7 OE2 Q8-Q15 OE3 Q16-Q23
0 Hi-Z 0 Hi-Z 0 Hi-Z
1 Enabled 1 Enabled 1 Enabled
Control Input Clock
CLK_SEL CLK0, nCLK0 CLK1, nCLK1
0 Selected De-selected
1 De-selected Selected
Inputs Outputs
Input to Output Mode Polarity
OE1, OE2, OE3 CLK nCLK Q0 thru Q23
1 0 1 LOW Differential to Single Ended Non Inverting
1 1 0 HIGH Differential to Single Ended Non Inverting
1 0 Biased; NOTE 1 LOW Single Ended to Differential Non Inverting
1 1 Biased; NOTE 1 HIGH Single Ended to Differential Non Inverting
1 Biased; NOTE 1 0 HIGH Single Ended to Differential Inverting
1 Biased; NOTE 1 1 LOW Single Ended to Differential Inverting
NOTE 1: Please refer to the Application Information section on page 13, Figure 8, which discusses wiring the differential input
to accept single ended levels.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

8344BYILF

Mfr. #:
Buy 8344BYILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 24 LVCMOS OUT BUFFER
Lifecycle:
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