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APS11205LLHALX

P1-P3P4-P6P7-P9P10-P12P13-P13
High-Temperature Hall-Effect Switch
for Low Voltage Applications
APS11205
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
OPERATION
The output of the APS11205 switches low (turns on) when a
south-polarity magnetic field perpendicular to the Hall element
exceeds the operate point threshold, B
OP
(see Figure 1). After
turn-on, the output transistor is capable of continuously sink-
ing up to 30 mA. When the magnetic field is reduced below the
release point, B
RP
, the device output goes high (turns off).
B
OP
B
RP
B
HYS
Switch to Low
Switch to High
B+
(south)
0
0
Figure 1: Device Switching Behavior
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength.
The difference in the magnetic operate and release points is the
hysteresis, B
HYS ,
of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
POWER-ON BEHAVIOR
Device power-on occurs once t
ON
has elapsed. During the
time prior to t
ON
, and after V
CC
≥ V
CC
(min), the output state is
V
OUT(SAT)
. After t
ON
has elapsed, the output will correspond with
the applied magnetic field for B > B
OP
or B < B
RP
. See Figure 2
for an example.
Powering-on the device in the hysteresis range (less than B
OP
and
higher than B
RP
) will give an output state of V
OUT(OFF)
. The cor-
rect state is attained after the first excursion beyond B
OP
or B
RP
.
t
t
V
V
CC
(min)
t
ON
0
Output State
Undefined for
V
CC
< V
CC
(min)
POS
V
OUT (SAT)
V
OUT(OFF)
V
V
OUT
V
CC
Key
POS
B > B
OP
B < B
RP
, B
RP
< B < B
OP
Figure 2: Power-On Sequence and Timing
FUNCTIONAL DESCRIPTION
High-Temperature Hall-Effect Switch
for Low Voltage Applications
APS11205
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Applications
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
under harsh environmental conditions and to reduce noise from
internal circuitry. As is shown in Figure 3, a 0.1 µF capacitor is
typical.
Extensive applications information for Hall-effect devices is
available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009
All are provided on the Allegro website:
www.allegromicro.com
C
BYP
APS11205
VOUT
GND
0.1 µF
VCC
Output
R
L
V
S
Figure 3: Typical Application Circuit
High-Temperature Hall-Effect Switch
for Low Voltage Applications
APS11205
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Amp
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small-signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The Allegro technique, dynamic quadrature offset cancellation,
removes key sources of the output drift induced by temperature
and package stress. This offset reduction technique is based on
a signal modulation-demodulation process. Figure 4: Model of
Chopper Stabilization Circuit (Dynamic Offset Cancellation)
illustrates how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation.
The subsequent demodulation acts as a modulation process for
the offset causing the magnetically induced signal to recover its
original spectrum at baseband while the DC offset becomes a
high-frequency signal. Then, using a low-pass filter, the signal
passes while the modulated DC offset is suppressed. Allegro’s
innovative chopper stabilization technique uses a high-frequency
clock. The high-frequency operation allows a greater sampling
rate that produces higher accuracy, reduced jitter, and faster sig-
nal processing. Additionally, filtering is more effective and results
in a lower noise analog signal at the sensor output. Devices such
as the A11205 that use this approach have an extremely stable
quiescent Hall output voltage, are immune to thermal stress,
and have precise recoverability after temperature cycling. This
technique is made possible through the use of a BiCMOS process
which allows the use of low-offset and low-noise amplifiers in
combination with high-density logic and sample-and-hold circuits
Figure 4: Model of Chopper Stabilization Circuit
(Dynamic Offset Cancellation)
CHOPPER STABILIZATION
P1-P3P4-P6P7-P9P10-P12P13-P13

APS11205LLHALX

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