AD790
REV.
–6–
CIRCUIT DESCRIPTION
The AD790 possesses the overall characteristics of a standard
monolithic comparator: differential inputs, high gain and a logic
output. However, its function is implemented with an architec-
ture which offers several advantages over previous comparator
designs. Specifically, the output stage alleviates some of the limi-
tations of classic “TTL” comparators and provides a symmetric
output. A simplified representation of the AD790 circuitry is
shown in Figure 5.
A1
A2
Av
OUTPUT
GAIN STAGE
OUTPUT STAGE
Q2
Q1
–
+
–
+
–
+
IN
+
IN
–
V
LOGIC
GND
Figure 5. AD790 Block Diagram
The output stage takes the amplified differential input signal and
converts it to a single-ended logic output. The output swing is
defined by the pull-up PNP and the pull-down NPN. These pro-
duce inherent rail-to-rail output levels, compatible with CMOS
logic, as well as TTL, without the need for clamping to internal
bias levels. Furthermore, the pull-up and pull-down levels are
symmetric about the center of the supply range and are refer-
enced off the V
LOGIC
supply and ground. The output stage has
nearly symmetric dynamic drive capability, yielding equal rise
and fall times into subsequent logic gates.
Unlike classic TTL or CMOS output stages, the AD790 circuit
does not exhibit large current spikes due to unwanted current
flow between the output transistors. The AD790 output stage
has a controlled switching scheme in which amplifiers A1 and
A2 drive the output transistors in a manner designed to reduce
the current flow between Q1 and Q2. This also helps minimize
the disturbances feeding back to the input which can cause
troublesome oscillations.
The output high and low levels are well controlled values defined
by V
LOGIC
(5 V), ground and the transistor equivalent Schottky
clamps and are compatible with TTL and CMOS logic require-
ments. The fanout of the output stage is shown in TPC 3 for
standard LSTTL or HCMOS gates. Output drive behavior vs.
capacitive load is shown in TPC 2.
HYSTERESIS
The AD790 uses internal feedback to develop hysteresis about
the input reference voltage. Figure 6 shows how the input offset
voltage and hysteresis terms are defined. Input offset voltage
(V
OS
) is the difference between the center of the hysteresis
range and the ground level. This can be either positive or nega-
tive. The hysteresis voltage (V
H
) is one-half the width of the
V
OH
V
OL
H
V
= HYSTERESIS VOLTAGE
H
V
0
H
V
OUT
IN
+
V
OS
V
OS
= INPUT OFFSET VOLTAGE
2
3
7
IN
+
OUT
V
GND
Figure 6. Hysteresis Definitions (N, Q Package Pinout)
hysteresis range. This built-in hysteresis allows the AD790 to
avoid oscillation when an input signal slowly crosses the ground
level.
SUPPLY VOLTAGE CONNECTIONS
The AD790 may be operated from either single or dual supply
voltages. Internally, the V
LOGIC
circuitry and the analog front-
end of the AD790 are connected to separate supply pins. If dual
supplies are used, any combination of voltages in which +V
S
≥
V
LOGIC
– 0.5 V and –V
S
≤ 0 may be chosen. For single supply
operation (i.e., +V
S
= V
LOGIC
), the supply voltage can be oper-
ated between 4.5 V and 7 V. Figure 7 shows some other examples
of typical supply connections possible with the AD790.
BYPASSING AND GROUNDING
Although the AD790 is designed to be stable and free from
oscillations, it is important to properly bypass and ground the
power supplies. Ceramic 0.1 µF capacitors are recommended
and should be connected directly at the AD790’s supply pins.
These capacitors provide transient currents to the device during
comparator switching. The AD790 has three supply voltage
pins, +V
S
, –V
S
and V
LOGIC
. It is important to have a common
ground lead on the board for the supply grounds and the GND
pin of the AD790 to provide the proper return path for the
supply current.
LATCH OPERATION
The AD790 has a latch function for retaining input information
at the output. The comparator decision is “latched” and the
output state is held when Pin 5 is brought low. As long as Pin 5
is kept low, the output remains in the high or low state, and
does not respond to changing inputs. Proper capture of the
input signal requires that the timing relationships shown in
Figure 4 are followed. Pin 5 should be driven with CMOS or
TTL logic levels.
The output of the AD790 will respond to the input when Pin 5
is at a high logic level. When not in use, Pin 5 should be connected
to the positive logic supply. When using dual supplies, it is rec-
ommended that a 510 Ω resistor be placed in series with Pin 5
and the driving logic gate to limit input currents during powerup.
