ICS8536-01 Data Sheet CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
ICS8536AG-01 REVISION B AUGUST 17, 2012 7 ©2012 Integrated Device Technology, Inc.
ADDITIVE PHASE JITTER
Additive Phase Jitter
@ 155.52MHz (12kHz to 20MHz)
= 0.19ps typical
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues relating to the limitations of the measurement
equipment. The noise floor of the equipment can be higher or
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
lower than the noise floor of the device. Additive phase noise is
dependent on both the noise floor of the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
ICS8536-01 Data Sheet CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
ICS8536AG-01 REVISION B AUGUST 17, 2012 8 ©2012 Integrated Device Technology, Inc.
PARAMETER MEASUREMENT INFORMATION
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT 2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
V
EE
-1.3V±0.165V
SCOPE
Qx
nQx
LVPECL
V
EE
2V
-0.5V ± 0.125V
V
CC
2V
V
CC
DIFFERENTIAL INPUT LEVELS
tsk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLK1
nCLK1
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIODPART-TO-PART SKEW
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Q0:Q5
nQ0:nQ5
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
ICS8536-01 Data Sheet CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
ICS8536AG-01 REVISION B AUGUST 17, 2012 9 ©2012 Integrated Device Technology, Inc.
OUTPUT RISE/FALL TIME
t
PD
PROPAGATION DELAY (LVCMOS INPUT)
20%
80%
80%
20%
t
R
t
F
V
SWING
CLK1
nCLK1
Q0:Q5
nQ0:nQ5
PROPAGATION DELAY (DIFFERENTIAL INPUT)
t
PD
CLK0
Q0:Q5
nQ0:nQ5
Q0:Q5
nQ0:nQ5

8536AG-01LF

Mfr. #:
Manufacturer:
Description:
Clock Buffer 1:6 XTAL & LVCMOS to 3.3V Fanout Buffe
Lifecycle:
New from this manufacturer.
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