NB3N502DG

© Semiconductor Components Industries, LLC, 2012
May, 2012 Rev. 1
1 Publication Order Number:
NB3N502/D
NB3N502
14 MHz to 190 MHz PLL
Clock Multiplier
Description
The NB3N502 is a clock multiplier device that generates a low jitter,
TTL/CMOS level output clock which is a precise multiple of the
external input reference clock signal source. The device is a cost
efficient replacement for the crystal oscillators commonly used in
electronic systems. It accepts a standard fundamental mode crystal or
an external reference clock signal. PhaseLockedLoop (PLL) design
techniques are used to produce an output clock up to 190 MHz with a
50% duty cycle. The NB3N502 can be programmed via two select
inputs (S0, S1) to provide an output clock (CLKOUT) at one of six
different multiples of the input frequency source, and at the same time
output the input aligned reference clock signal (REF).
Features
Clock Output Frequency up to 190 MHz
Operating Range: V
DD
= 3 V to 5.5 V
Low Jitter Output of 15 ps One Sigma (rms)
Zero ppm Clock Multiplication Error
45% 55% Duty Cycle
25 mA TTLlevel Drive Outputs
Crystal Reference Input Range of 5 27 MHz
Input Clock Frequency Range of 2 50 MHz
Available in 8pin SOIC Package or in Die Form
Full Industrial Temperature Range 40°C to 85°C
These are PbFree Devices
÷ M
Feedback
V
DD
Multiplier
Select
S1
Reference
Clock
REF
Phase
Detector
Charge
Pump
Crystal
Oscillator
X2
÷ P
X1/CLK
CLKOUT
Figure 1. NB3N502 Logic Diagram
GND
S0
TTL/
CMOS
Output
VCO
TTL/
CMOS
Output
Device Package Shipping
ORDERING INFORMATION
NB3N502DG SOIC8
(PbFree)
98 Units / Rail
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAM
http://onsemi.com
3N502 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
3N502
ALYW
G
1
8
NB3N502DR2G SOIC8
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
8
NB3N502
http://onsemi.com
2
Figure 2. Pin Configuration (Top View)
CLKOUT
S0
S1
X2
X1/CLK
V
DD
GND
REF
1
2
3
45
6
7
8
Table 1. CLOCK MULTIPLIER SELECT TABLE
S1* S0** Multiplier
L L 2X
L H 5X
M L 3X
M H 3.33X
H L 4X
H H 2.5X
L = GND
H = V
DD
M = OPEN (unconnected)
* Pin S1 defaults to M when left open
** Pin S0 defaults to H when left open
Table 2. OUTPUT FREQUENCY EXAMPLES
Output Frequency (MHz) 20 25 33.3 48 50 54 64 66.66 75 100 108 120 135
Input Frequency (MHz) 10 10 10 16 20 13.5 16 20 15 20 27 24 27
S1, S0 0 ,0 1, 1 M, 1 M, 0 1, 1 1, 0 1, 0 M, 1 0, 1 0, 1 1, 0 0, 1 0, 1
Table 3. PIN DESCRIPTION
Pin # Name I/O Description
1 X1/CLK Input Crystal or External Reference Clock Input
2 V
DD
Power Supply Positive Supply Voltage (3 V to 5.5 V)
3 GND Power Supply 0 V Ground.
4 REF CMOS/TTL Output Buffered Crystal Oscillator Clock Output
5 CLKOUT CMOS/TTL Output Clock Output
6 S0 CMOS/TTL Input Multiplier Select Pin Connect to V
DD
or GND. Internal Pullup Resistor.
7 S1 Threelevel Input Multiplier Select Pin Connect to V
DD
, GND or Float to M.
8 X2 Crystal Input Crystal Input Do Not Connect when Providing an External Clock Reference
Table 4. ATTRIBUTES
Characteristic Value
ESD Protection Human Body Model
Machine Model
> 8 kV
> 600 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 6700 Devices
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
NB3N502
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3
Table 5. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
V
DD
Positive Power Supply GND = 0 V 7 V
V
I
Input Voltage GND – 0.5 = V
I
=
V
DD
+ 0.5
V
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (JunctiontoAmbient) 0 LFPM
500 LFPM
SOIC8
SOIC8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) (Note 1) SOIC8 41 to 44 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power).
Table 6. DC CHARACTERISTICS (V
DD
= 3 V to 5.5 V unless otherwise noted, GND = 0 V, T
A
= 40°C to +85°C) (Note 2)
Symbol Characteristic Min Typ Max Unit
I
DD
Power Supply Current
(unloaded CLKOUT operating at 100 MHz with 20 MHz crystal)
20 mA
V
OH
Output HIGH Voltage I
OH
= 25 mA TTL High 2.4 V
V
OL
Output LOW Voltage I
OL
= 25 mA 0.4 V
V
IH
Input HIGH Voltage, CLK only (pin 1) (V
DD
/ 2) + 1 V
DD
/ 2 V
V
IL
Input LOW Voltage, CLK only (pin 1) V
DD
/ 2 (V
DD
/ 2) 1 V
V
IH
Input HIGH Voltage, S0, S1 V
DD
– 0.5 V
V
IL
Input LOW Voltage, S0, S1 0.5 V
V
IM
Input level of S1 when open (Input Mid Point) V
DD
÷ 2 V
C
in
Input Capacitance, S0, S1 4 pF
I
SC
Output Short Circuit Current ± 70 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Parameters are guaranteed by characterization and design, not tested in production.
Table 7. AC CHARACTERISTICS (V
DD
= 3 V to 5.5 V unless otherwise noted, GND = 0 V, T
A
= 40°C to +85°C) (Note 3)
Symbol Characteristic Min Typ Max Unit
f
Xtal
Crystal Input Frequency 5 27 MHz
f
CLK
Clock Input Frequency 2 50 MHz
f
OUT
Output Frequency Range
V
DD
= 4.5 to 5.5 V (5.0 V ± 10%)
V
DD
= 3.0 to 3.6 V (3.3 V ± 10%)
14
14
190
120
MHz
MHz
DC Clock Output Duty Cycle at 1.5 V up to 190 MHz 45 50 55 %
t
jitter
(rms)
Period Jitter (RMS, 1 σ) 15 ps
t
jitter
(pktopk)
Total Period Jitter, (peaktopeak) ±40 ps
t
r
/t
f
Output rise/fall time (0.8 V to 2.0 V / 2.0 V to 0.8 V) 1 2 ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Parameters are guaranteed by characterization and design, not tested in production.

NB3N502DG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL PLL CLK MULTIPLIER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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