©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6520A
Rev. 1.0.5 7
FAN6520A Single Synchronous Buck PWM Controller
Figure 4. Soft-Start Interval
The FAN6520A incorporates a MOSFET shoot-through
protection method that allows a converter to both sink
and source current. Care should be exercised when
designing a converter with the FAN6520A when it is
known that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter regulating its input voltage. This means
that the converter is boosting current into the V
CC
rail,
which supplies the bias voltage to the FAN6520A. If this
current has nowhere to go—such as to other distributed
loads on the V
CC
rail, through a voltage limiting protec-
tion device, or other methods—the capacitance on the
V
CC
bus absorbs the current. This allows the voltage
level of the V
CC
rail to increase. If the voltage level of the
rail is boosted to a level that exceeds the maximum volt-
age rating of the FAN6520A, the IC experiences an irre-
versible failure and the converter is no longer
operational. Ensure that there is a path for the current to
follow, other than the capacitance on the rail, to prevent
this failure mode.
Application Information
Layout Considerations
In any high-frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. Use wide, short-printed traces to minimize inter-
connecting impedances. The critical components should
be located as close together as possible, using ground
plane construction or single-point grounding.
Figure 5. Printed Circuit Board Power and
Ground Planes or Islands
Figure 5 shows the critical power components of the con-
verter. To minimize voltage overshoot, the interconnect-
ing wires (indicated by heavy lines) should be part of a
ground or power plane in a printed circuit board. The
components shown in Figure 5 should be located as
close together as possible. Note that the capacitors C
IN
and C
OUT
may each represent numerous physical capac-
itors. Locate the FAN6520A within two inches of the Q1
and Q2 MOSFETs. The circuit traces for the MOSFETs’
gate and source connections from the FAN6520A must
be sized to handle up to 1A peak current.
Figure 5 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/OCSET pin and locate the
resistor, R
OSCET,
close to the COMP/OCSET pin
because the internal current source is only 20µA. Pro-
vide local V
CC
decoupling between the VCC and GND
pins. Locate the capacitor, CBOOT, as close as practical
to the BOOT and PHASE pins. All components used for
feedback compensation should be located as close to
the IC as practical.
Figure 6. PCB Small Signal Layout Guidelines
+V
OUT
Q2
LDRV
SW
HDRV
Q1
C
IN
L
OUT
C
OUT
LOAD
Vin
+V
OUT
Q2
VCC
SW
BOOT
L
OUT
C
OUT
LOAD
GND
C
BOOT
C
VCC
+5V
D
BOOT
FAN6520A
Q1
Vin
COMP/OCSET
R
OCSET
+5V
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6520A
Rev. 1.0.5 8
FAN6520A Single Synchronous Buck PWM Controller
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the reference voltage level. The
error amplifier (Error Amp) output (V
E/A
) is compared
with the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V
IN
at the SW node. The PWM wave is smoothed by the
output LC filter (L
OUT
and C
OUT
).
Figure 7. Voltage Mode Buck
Converter Compensation Design
The modulator transfer function is the small-signal trans-
fer function of V
OUT
/V
COMP
. This function is dominated
by a DC gain and the output filter (L
OUT
and C
OUT
), with
a double-pole break frequency at F
LC
and a zero at
F
ESR
. The DC gain of the modulator is the input voltage
(V
IN
) divided by the peak-to-peak oscillator voltage
(ΔV
OSC
. )
The following equations define the modulator break fre-
quencies as a function of the output LC filter:
The compensation network consists of the error amplifier
(internal to the FAN6520A) and the impedance networks
Z
IN
and Z
FB
. The goal of the compensation network is to
provide a closed-loop transfer function with the highest
0dB crossing frequency (F
0dB
) and adequate phase mar-
gin. Phase margin is the difference between the closed-
loop phase at F
0dB
and 180 degrees. The equations
below relate the compensation network’s poles, zeros,
and gain to the components (R1, R2, R3, C1, C2, and
C3), shown in Figure 7.
Use the following steps to locate the poles and zeros of
the compensation network:
1. Pick gain (R2/R1) for the desired converter band-
width.
2. Place the first zero below the filter’s double pole
(~75% F
LC
).
3. Place the second zero at filter’s double pole.
4. Place the first pole at the ESR zero.
5. Place the second pole at half the switching fre-
quency.
6. Check the gain against the error amplifier’s open-
loop gain.
7. Estimate phase margin. Repeat if necessary.
Figure 8 shows an asymptotic plot of the DC-DC con-
verter’s gain vs. frequency. The actual modulator gain
has a high gain peak due to the high Q factor of the out-
put filter and is not shown in Figure 8. Using the above
guidelines should give a compensation gain similar to
the curve plotted. The open-loop error amplifier gain
bounds the compensation gain. Check the compensation
gain at FP2 with the capabilities of the error amplifier.
The closed-loop gain is constructed on the graph of Fig-
ure 8 by adding the modulator gain (in dB) to the com-
pensation gain (in dB). This is equivalent to multiplying
the modulator transfer function by the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance net-
works Z
FB
and Z
IN
to provide a stable high bandwidth
overall loop. A stable control loop has a gain crossing
with a –20dB/decade slope and a phase margin greater
than 45°. Include worst-case component variations when
determining phase margin.
Z
FB
COMP
FB
+V
OUT
Q2
L
OUT
C
OUT
+5V
V
IN
SW
ESR
0.8V
ERROR
AMP
PWM
OSC
DETAILED COMPENSATION
COMPONENTS
COMP
FB
0.8V
ERROR
AMP
C1
R2
C3
R3
C2
R1
Z
IN
V
OUT
Z
FB
Z
IN
F
LC
1
2π LC×
-------------------------=
(3)
F
ESR
1
2π ESR× C×
------------------------------------=
(4)
F
Z1
1
2πR
2
C
1
----------------------=
(5)
F
P1
1
2πR
2
C
1
C
2
C
1
C
2
+
--------------------
⎝⎠
⎛⎞
-----------------------------------------=
(6)
F
Z2
1
2πC
3
R
1
R
3
+()
----------------------------------------=
(7)
F
P2
1
2πR
3
C
3
----------------------=
(8)
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6520A
Rev. 1.0.5 9
FAN6520A Single Synchronous Buck PWM Controller
Figure 8. Asymptotic Bode Plot of Converter Gain
An output capacitor is required to filter the output and
supply the load transient current. The filtering require-
ments are a function of the switching frequency and the
ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally
met with a mix of capacitors and careful layout.
Component Selection
Output Capacitors (C
OUT
)
Modern components and loads are capable of producing
transient load rates above 1A/ns. High-frequency capac-
itors initially supply the transient and slow the current
load rate seen by the bulk capacitors. Effective Series
Resistance (ESR) and voltage rating are typically the
prime considerations for the bulk filter capacitors, rather
than actual capacitance requirements. High-frequency
decoupling capacitors should be placed as close to the
power pins of the load as physically possible. Be careful
not to add inductance in the circuit board wiring that
could cancel the performance of these low-inductance
components. Consult with the load manufacturer on spe-
cific decoupling requirements. Use only specialized low-
ESR capacitors intended for switching-regulator applica-
tions for the bulk capacitors. The bulk capacitor’s ESR
determines the output ripple voltage and the initial volt-
age drop after a high slew-rate transient. An aluminum
electrolytic capacitor’s ESR value is related to the case
size with lower ESR available in larger case sizes; how-
ever, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Since ESL is not a specified parameter, work
with the capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable compo-
nent. Generally, multiple small-case electrolytic capaci-
tors perform better than a single large-case capacitor.
Output Inductor (L
OUT
)
The output inductor is selected to meet the output volt-
age ripple requirements and minimize the converter’s
response time to the load transient. The inductor value
determines the converter’s ripple current and the ripple
voltage is a function of the ripple current. The ripple volt-
age (ΔV) and current (ΔI) are approximated by the fol-
lowing equations:
Increasing the inductance value reduces the ripple cur-
rent and voltage, but also reduces the converter’s ability
to quickly respond to a load transient. One of the param-
eters limiting the converter’s response to a load transient
is the time required to change the inductor current.
Given a sufficiently fast control-loop design, the
FAN6520A provides either 0% or 100% duty cycle in
response to a load transient. The response time is the
time required to slew the inductor current from an initial
current value to the transient current level. During this
interval, the difference between the inductor current and
the transient current level must be supplied by the output
capacitor. Minimizing the response time can minimize
the output capacitance required.
Depending on whether there is a load application or a
load removal, the response time to a load transient
(I
STEP
) is different. The following equations give the
approximate response time interval for application and
removal of a transient load:
where T
RISE
is the response time to the application of a
positive I
STEP
and T
FALL
is the response time to a load
removal (negative I
STEP
). The worst-case response time
can be either at application or removal of load. Check
both of these equations at the minimum and maximum
output levels for the worst-case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the volt-
age overshoot across the MOSFETs. Use small ceramic
capacitors for high-frequency decoupling and bulk
capacitors to supply the current needed each time Q1
turns on. Place the small ceramic capacitors physically
close to the MOSFETs and between the drain of Q1 and
the source of Q2. The important parameters for the bulk
input capacitor are the voltage rating and the RMS cur-
rent rating. For reliable operation, select the bulk capaci-
tor with voltage and current ratings above the maximum
input voltage and the largest RMS current required by
the circuit. The capacitor voltage rating should be at least
100
80
60
40
20
0
-20
-40
-60
10 100 1K 10K 100K
FREQUENCY (Hz)
OPEN LOOP
ERROR AMP GAIN
COMPENSATION
GAIN
CLOSED LOOP
GAIN
MODULATOR
GAIN
20LOG
(V
IN
/DV
OSC
)
20LOG
(R
2
/R
1
)
F
Z1
F
Z2
F
P1
F
LC
F
ESR
F
P2
GAIN (dB)
1M 10M
ΔI
V
IN
V
OUT
F
SW
L×
------------------------------
⎝⎠
⎜⎟
⎛⎞
V
OUT
V
IN
--------------
×=
ΔVESRΔI×
(9)
T
RISE
LI
STEP
×
V
IN
V
OUT
------------------------------=
(10)
T
FALL
LI
STEP
×
V
OUT
------------------------
=
(11)

FAN6520AM

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Switching Controllers Single Synchronous Buck PWM Controller
Lifecycle:
New from this manufacturer.
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