TVS8501V5MUT5G

TVS8501V5
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4
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 4. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 5 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
Figure 4. Simplified Schematic of a Typical TLP
System
DUT
L
S
÷
Oscilloscope
Attenuator
10 MW
V
C
V
M
I
M
50 W Coax
Cable
50 W Coax
Cable
Figure 5. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
TVS8501V5
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5
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 6. IEC61000−4−2 Spec
50 W
50 W
Cable
TVS
Oscilloscope
ESD Gun
Figure 7. Diagram of ESD Test Setup
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 8. 8 X 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0
020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
t
P
t
r
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE I
RSM
@ 8 ms
HALF VALUE I
RSM
/2 @ 20 ms
TVS8501V5
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6
PACKAGE DIMENSIONS
UDFN2 1.6x1.0, 1.1P
CASE 517CZ
ISSUE A
1
2X
0.58
DIMENSIONS: MILLIMETERS
1.00
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2X
RECOMMENDED
1.70
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
B
E
D
BOTTOM VIEW
b
2X
2X
0.08 C
PIN ONE
REFERENCE
TOP VIEW
2X
0.08 C
A
A1
0.05 C
0.05 C
C
SEATING
PLANE
SIDE VIEW
L
1
DIM MIN MAX
MILLIMETERS
A 0.45 0.55
A1 −− 0.05
b 0.85 0.95
D 1.60 BSC
E 1.00 BSC
e 1.10 BSC
L 0.35 0.45
e/2
e
A
M
0.07 BC
A
M
0.07 BC
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P
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TVS8501V5/D
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TVS8501V5MUT5G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors 5V TVS IN UDFN2
Lifecycle:
New from this manufacturer.
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