LTC1456IS8#PBF

4
LTC1456
TYPICAL PERFORMANCE CHARACTERISTICS
UW
CODE
0
0.5
DNL (LSB)
0.4
0.2
0.1
0
0.5
0.2
1024 2048 2560
1456 G01
0.3
0.3
0.4
0.1
512 1536 3072 3584 4095
Differential Nonlinearity (DNL)
Minimum Supply Headroom for
Full Output Swing vs Load Current
LOAD CURRENT (mA)
0
0.8
1.0
1.2
15 25
1456 G03
0.6
0.4
510
20 30
0.2
0
V
CC
– V
OUT
(V)
1.4
V
OUT
< 1LSB
CODE: ALL 1s
V
OUT
= 4.095V
CODE
0
2.0
INL ERROR (LSB)
–1.6
0.8
0.4
0
2.0
0.8
1024 2048 2560
1456 G02
–1.2
1.2
1.6
0.4
512 1536 3072 3584 4095
Integral Nonlinearity (INL)
Minimum Output Voltage
vs Output Sink Current
OUTPUT SINK CURRENT (mA)
0
0
OUTPUT PULL-DOWN VOLTAGE (mV)
100
300
400
500
700
2
10
14
1456 G04
200
600
8
18
20
4
6
12 16
125°C
25°C
–55°C
Supply Current
vs Logic Input Voltage Output Swing vs Load Resistance
LOAD RESISTANCE ()
10
2.5
OUTPUT SWING (V)
3.0
3.5
4.0
4.5
100 1k 10k
1456 G06
2.0
1.5
0.5
0
1.0
V
CC
R
L
CODE: ALL 0s
LOAD RESISTANCE ()
10
2.5
OUTPUT SWING (V)
3.0
3.5
4.0
4.5
100 1k 10k
1456 G07
2.0
1.5
0.5
0
1.0
R
L
CODE: ALL 1s
Output Swing vs Load Resistance Offset Voltage vs Temperature
TEMPERATURE (°C)
–55
0.3
OFFSET VOLTAGE (mV)
0.4
0.5
0.6
0.7
0.9
–25
53565
1456 G08
95 125
0.8
Supply Current vs Temperature
TEMPERATURE (°C)
–55
SUPPLY CURRENT (µA)
510
530
550
65
1456 G09
490
470
500
520
540
480
460
450
–25
5
35
95
125
V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5V
LOGIC INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
1.210
1.480
1.750
4
1456 G05
0.940
0.670
1.075
1.345
1.615
0.805
0.535
0.400
1
2
3
0.5 4.5
1.5
2.5
3.5
5
ALL DIGITAL INPUTS
TIED TOGETHER
5
LTC1456
CLK (Pin 1): The Serial Interface Clock. Internal Schmitt
trigger on this input allows direct optocoupler interface.
D
IN
(Pin 2): The Serial Interface Data. Data on the D
IN
pin
is latched into the shift register on the rising edge of the
serial clock.
CS/LD (Pin 3): The Serial Interface Enable and Load
Control. When CS/LD is low the CLK signal is enabled, so
the data can be clocked in. When CS/LD is pulled high,
data is loaded from the shift register into the DAC
register, updating the DAC output. When CS/LD is high
the CLK is disabled internally.
PIN FUNCTIONS
UUU
D
OUT
(Pin 4): The Output of the Shift Register Which
Becomes Valid on the Rising Edge of the Serial Clock.
GND (Pin 5): Ground.
CLR (Pin 6): The Clear Input. When pulled low, this pin
asynchronously clears the internal shift and DAC registers
to zero scale. Should be tied high for normal operation.
V
OUT
(Pin 7): The Buffered DAC Output.
V
CC
(Pin 8): The Positive Supply Input. 4.5V V
CC
5.5V.
Requires a bypass capacitor to ground.
B11
MSB
B10
t
1
t
9
B1
t
6
B0
LSB
B11
CURRENT WORD
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1456 TD
B0
PREVIOUS WORD
B11
PREVIOUS WORD
B10
B1
B0
W
IDAGRA
B
L
O
C
K
DAC
REGISTER
LD
12-BIT
SHIFT
REGISTER
POWER-ON
RESET
1146 BD
CLK
1
D
IN
2
D
OUT
4
V
OUT
7
CLR
6
GND
5
V
CC
8
3
CS/LD
12-BIT
DAC
2.048V
+
TI I G DIAGRA
WU W
6
LTC1456
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2
n
) that divide the full-scale range. The resolution
does not imply linearity.
Full-Scale Voltage (V
FS
): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
): The theoretical voltage at the
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
V
OS
= V
OUT
– [(Code • V
FS
)/(2
n
– 1)]
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
LSB = (V
FS
– V
OS
)/(2
n
– 1) = (V
FS
– V
OS
)/4095
LSB = 4.095/4095 = 1mV
DEFI ITIO S
UU
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end-points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset speci-
fication. The INL error at a given input code is calculated
as follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/4095)]/LSB
V
OUT
= The output voltage of the DAC measured at
the given input code
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:
DNL = (V
OUT
– LSB)/LSB
V
OUT
= The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
DAC CODE
1456 F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
Figure 1. Effect of Negative Offset

LTC1456IS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Single 12-Bit Vout DAC w/Clear
Lifecycle:
New from this manufacturer.
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