M27C801 Device description
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ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4 System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I
CC
, has three segments that are of interest to
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E
. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor be used on every device between V
CC
and V
SS
. This should
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
2.5 Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C801 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0' will be programmed, both '1's and '0's can be present in the data word. The
only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C801 is in the programming mode when V
PP
input is at 12.75V and E is pulsed to V
IL
.
The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL. V
CC
is specified to be 6.25V ± 0.25V.
2.6 Presto IIB programming algorithm
Presto IIB Programming Algorithm allows the whole array to be programmed with a
guaranteed margin, in a typical time of 52.5 seconds. This can be achieved with
STMicroelectronics M27C801 due to several design innovations to improve programming
efficiency and to provide adequate margin for reliability. Before starting the programming the
internal Margin Mode circuit is set in order to guarantee that each cell is programmed with
enough margin. Then a sequence of 50 µs program pulses are applied to each byte until a
correct Verify occurs (see Figure 4). No overprogram pulses are applied since the Verify in
Margin Mode provides the necessary margin.
Obsolete Product(s) - Obsolete Product(s)
