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71T75902S85BG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
6.42
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
19
Timing Waveform of CEN Operation
(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur.
All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
t
H
E
t
S
E
R
/W
A
1
A
2
C
L
K
C
E
N
A
D
V
/LD
A
D
D
R
E
S
S
C
E
1
, C
E
2
(2)
B
W
1
- B
W
4
O
E
D
A
T
A
O
U
T
Q
(A
1
)
t
C
D
C
Q
(A
3
)
t
C
D
t
C
LZ
Q
(A
1
)
Q
(A
4
)
t
C
D
t
C
D
C
t
C
H
Z
D
(A
2
)
t
S
D
t
H
D
t
C
H
t
C
L
t
C
Y
C
t
H
C
t
S
C
A
4
A
5
t
H
A
D
V
t
S
A
D
V
t
H
W
t
S
W
t
H
A
t
S
A
A
3
t
H
B
t
S
B
D
A
T
A
IN
531
9
drw
09
B
(A
2
)
,
6.4220
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation
(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the
deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
R
/W
A
1
C
LK
A
D
V
/LD
A
D
D
R
E
S
S
C
E
1
, C
E
2
(2)
O
E
D
A
T
A
O
U
T
Q
(A
1
)
Q
(A
2
)
Q
(A
4
)
t
C
LZ
Q
(A
5
)
t
C
D
t
C
H
Z
t
C
D
C
D
(A
3
)
t
S
D
t
H
D
t
C
H
t
C
L
t
C
Y
C
t
H
C
t
S
C
A
5
A
3
t
S
B
D
A
T
A
IN
t
H
E
t
S
E
A
2
t
H
A
t
S
A
A
4
t
H
W
t
S
W
t
H
B
C
E
N
t
H
A
D
V
t
S
A
D
V
5319
drw
10
B
W
1
- B
W
4
B
(A
3
)
,
,
6.42
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
21
JTAG Interface Specification
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
(
3)
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
M5319 drw 01
x
Symbol
Parameter
Min.
Max.
Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
JTAG Clock HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
5
(1 )
ns
t
JF
JTAG Clock Fall Time
____
5
(1 )
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
JTAG Data Output
____
20 ns
t
JDC
JTAG Data Output Hold 0
____
ns
t
JS
JTAG Setup 25
____
ns
t
JH
JTAG Hold 25
____
ns
I5319 tbl 01
Register Name
Bit Size
Instruction (IR) 4
Bypass (BYR) 1
JTAG Identification (JIDR) 32
Boundary Scan (BSR) Note (1)
I5319 tbl 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JTAG AC Electrical
Characteristics
(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

71T75902S85BG8

Mfr. #:
Buy 71T75902S85BG8
Manufacturer:
IDT
Description:
SRAM X18 18M 2.5V CORE ZBT SLO
Lifecycle:
New from this manufacturer.
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