5
FN9056.11
September 29, 2015
Functional Pin Description
14 LD (SOIC)
TOP VIEW
16 LD 5X5 (QFN)
TOP VIEW
VCC
This pin provides the bias supply for the ISL6527, ISL6527A.
Connect a well-decoupled 3.3V supply to this pin.
COMP and FB
COMP and FB are two of the three available external pins of
the error amplifier. The FB pin is the inverting input of the
internal error amplifier and the COMP pin is the error
amplifier output. These pins are used to compensate the
voltage-control feedback loop of the converter.
REF_IN
This pin is the third available external pin of the error
amplifier and represents the non-inverting input to the error
amplifier. Connect the desired reference voltage to this pin.
Voltage applied to this pin must not exceed 1.5V.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
upper MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
LGATE
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.
OCSET/SD
Connect a resistor (R
OCSET
) from this pin to the drain of the
upper MOSFET (V
IN
). R
OCSET
, an internal 20µA current
source (I
OCSET
), and the upper MOSFET ON-resistance
(r
DS(ON)
) set the converter overcurrent (OC) trip point
according to Equation 1:
An overcurrent trip cycles the soft-start function.
Pulling OCSET/SD to a voltage level below 0.8V disables
the controller. Disabling the ISL6527, ISL6527A causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm.
CT1 and CT2
These pins are the connections for the external charge
pump capacitor. A minimum of a 0.1µF ceramic capacitor is
recommended for proper operation of the IC.
CPVOUT
This pin represents the output of the charge pump. The
voltage at this pin is the bias voltage for the IC. Connect a
decoupling capacitor from this pin to ground. The value of
the decoupling capacitor should be at least 10x the value of
the charge pump capacitor. This pin may be tied to the
bootstrap circuit as the source for creating the BOOT
voltage.
CPGND
This pin represents the signal and power ground for the
charge pump. Tie this pin to the ground island/plane through
the lowest impedance connection available.
12
14
13
4
3
2
1
LGATE
CPVOUT
UGATE
PHASE
VCC
BOOT
GND
CT1
11
7
6
5
9
8
10
CT2
OCSET/SD
FB
CPGND
REF_IN
COMP
1
3
4
15
CPVOUT
CT1
CT2
OCSET/SD
LGATE
GND
UGATE
BOOT
16 14 13
2
12
10
9
11
6578
PHASE
VCC
CPGND
NC
NC
FB
COMP
REF_IN
I
PEAK
I
OCSET
xR
OCSET
r
DS ON
-------------------------------------------------
=
(EQ. 1)
ISL6527, ISL6527A
