RT9166/A
10
DS9166/A-23 June 2012www.richtek.com
©
Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
PCB Layout
Good board layout practices must be used or instability
can be induced because of ground loops and voltage drops.
The input and output capacitors MUST be directly
connected to the input, output, and ground pins of the
device using traces which have no other currents flowing
through them.
The best way to do this is to layout C
IN
and C
OUT
near the
device with short traces to the V
IN
, V
OUT
, and ground pins.
The regulator ground pin should be connected to the
external circuit ground so that the regulator and its
capacitors have a “single point ground”.
It should be noted that stability problems have been seen
in applications where “vias” to an internal ground plane
were used at the ground points of the device and the input
and output capacitors. This was caused by varying ground
potentials at these nodes resulting from current flowing
through the ground plane. Using a single point ground
technique for the regulator and it’ s capacitors fixed the
problem. Since high current flows through the traces going
into V
IN
and coming from V
OUT
, Kelvin connect the capacitor
leads to these pins so there is no voltage drop in series
with the input and output capacitors.
Optimum performance can only be achieved when the
device is mounted on a PC board according to the diagram
below :
be calculated by following formula :
P
D (MAX)
= (T
J(MAX)
− T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125°C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance.
For recommended operating conditions specification,
where T
J(MAX)
is the maximum junction temperature of the
die (125°C) and T
A
is the operated ambient temperature.
The junction to ambient thermal resistance θ
JA
is layout
dependent. For SOT-23-3 packages, the thermal
resistance θ
JA
is 250°C/W on the standard JEDEC 51-3
single-layer thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by following
formula :
P
D (MAX)
= ( 125°C − 25°C) / 250°C/W = 0.400W for
SOT-23-3 packages
P
D (MAX)
= ( 125°C − 25°C) / 175°C/W = 0.571W for
SOT-89 packages
P
D (MAX)
= ( 125°C − 25°C) / 135°C/W = 0.740W for
SOT-223 packages
P
D (MAX)
= ( 125°C − 25°C) / 68°C/W = 1.470W for
TO-252 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. Figure 1 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power allowed.
Figure 1. Derating Curve of Maximum Power Dissipation
Figure 2. SOT-23-3 Board Layout
V
IN
GND
V
OUT
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (mW)
SOT-223
SOT-89
SOT-23-3
Single Layer PCB
TO-252
