–3–REV. 0
AD7729
Parameter AD7729A Units Test Conditions/Comments
LOGIC INPUTS
V
INH
, Input High Voltage V
DD
– 0.8 V min
V
INL
, Input Low Voltage 0.8 V max
I
IH
, Input Current 10 µA max
C
IN
, Input Capacitance 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage V
DD
– 0.4 V min |I
OUT
| < 100 µA
V
OL
, Output Low Voltage 0.4 V max |I
OUT
| < 100 µA
I
OZL
, Low Level Output Three-State Leakage Current 10 µA max
I
OZH
, High Level Output Three-State Leakage Current 10 µA max
POWER SUPPLIES
AVDD1, AVDD2 2.7/3.3 V min/max
DVDD1, DVDD2 2.7/3.3 V min/max
I
DD
See Table I
NOTES
1
Operating Temperature Range: 40°C to +105°C. Therefore, T
MIN
= –40°C and T
MAX
= +105°C.
2
During power-down, the AUXDAC has an output resistance of 30 k approximately to AGND.
Specifications subject to change without notice.
Table I. Current Summary (AVDD1 = AVDD2 = DVDD1 = DVDD2 = +3.3 V, RxPOWER1 = 0, RxPOWER0 = 1)
Internal External
Analog Digital Interface Total
Current Current Current Current MCLK
Conditions (typ) (typ) (typ) (max) BSE ASE ON Comments
ADCs On Only 4.2 3.4 4 13.5 1 0 YES REFOUT Enabled, BSCLK = MCLK
AUXDAC On Only 2 0.86 0.1 3.4 0 1 YES REFOUT Disabled, ASCLK = MCLK/48
REFCAP On Only 0.7 0.0001 0.002 1.1 0 0 NO REFOUT Disabled
REFCAP and
REFOUT On Only 1 0.0001 0.002 1.7 0 0 NO REFOUT Enabled
All Sections Off 0.0001 0.04 0.015 0.1 0 0 YES MCLK Active Levels Equal to 0 V and DVDD
All Sections Off 0.0001 0.0001 0.005 0.05 0 0 NO Digital Inputs Static and Equal to 0 V or
DVDD
The above values are in mA.
R
L
10kV
C
L
50pF
Figure 1. AUXDAC Load Equivalent Circuit
AD7729
–4 REV. 0
TIMING CHARACTERISTICS
Limit at
Parameter T
A
= –40C to +105C Units Description
AUXILIARY FUNCTIONS
Clock Signals See Figure 2.
t
1
76 ns min MCLK Period
t
2
30.4 ns min MCLK Width Low
t
3
30.4 ns min MCLK Width High
t
4
t
1
ns min ASCLK Period. See Figures 4 and 6.
t
5
0.4 × t
1
ns min ASCLK Width Low
t
6
0.4 × t
1
ns min ASCLK Width High
t
10
20 ns min ASDI/ASDIFS Setup Before ASCLK Low
t
11
10 ns min ASDI/ASDIFS Hold After ASCLK Low
t
12
15 ns max ASDOFS Delay from ASCLK High
t
13
0 ns min ASDOFS Hold After ASCLK High
t
14
0 ns min ASDO Hold After ASCLK High
t
15
15 ns max ASDO Delay from ASCLK High
t
16
10 ns min ASDIFS Low to ASDI LSB Read by ASPORT
t
17
t
4
+ 15 ns min Interval Between Consecutive ASDIFS Pulses
Receive Section
Clock Signals See Figures 5 and 7.
t
7
t
1
ns min BSCLK Period
t
8
0.4 × t
1
ns min BSCLK Width Low
t
9
0.4 × t
1
ns min BSCLK Width High
t
18
20 ns min BSDI/BSDIFS Setup Before BSCLK Low
t
19
10 ns min BSDI/BSDIFS HoldAfter BSCLK Low
t
20
15 ns max BSDOFS Delay from BSCLK High
t
21
0 ns min BSDOFS Hold After BSCLK High
t
22
0 ns min BSDO Hold After BSCLK High
t
23
15 ns max BSDO Delay from BSCLK High
t
24
10 ns min BSDIFS Low to ASDI LSB Read by BSPORT
t
25
t
7
+ 15 ns min Interval Between Consecutive BSDIFS Pulses
ASCLK = MCLK/(2 × ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz.
BSCLK = MCLK/(2 × BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz.
Specifications subject to change without notice.
(AVDD1 = AVDD2 = +3 V 10%; DVDD1 = DVDD2 = +3 V 10%; AGND = DGND = 0 V;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Table II. Receive Section Signal Ranges
Baseband Section Signal Range
V
REFCAP
1.3 V ± 5%
V
REFOUT
1.3 V ± 10%
ADC
ADC Signal Range 2 V
REFCAP
V
BIAS
Differential Input V
REFCAP
/2 to (AVDD1 – V
REFCAP
/2)
Single-Ended Input V
REFCAP
to (AVDD1 – V
REFCAP
)
Signal Range
Differential V
BIAS
± V
REFCAP
/2
Single-Ended V
BIAS
± V
REFCAP
Table III. Auxiliary Section Signal Ranges
AUXDAC Signal Range
Output Code
Code 000 2/32 × V
REFCAP
Code 3FF 2 V
REFCAP
AD7729
–5–REV. 0
TIMING DIAGRAMS
t
10
ASE (I)
ASCLK (O)
ASDIFS (I)
ASDOFS (O)
ASDI (I)
ASDO (O)
THREE-STATE
THREE-STATE
THREE-STATE
D9 D8
A1 A0
D9 D8
D7
D8D9
A0
A1
A2
D9
t
10
t
11
t
13
t
12
t
14
t
15
t
16
NOTE
I = INPUT, O = OUTPUT
t
17
t
11
Figure 6. Auxiliary Serial Port ASPORT
t
18
BSE (I)
BSCLK (O)
BSDIFS (I)
BSDOFS (O)
BSDI (I)
BSDO (O)
THREE-STATE
THREE-STATE
THREE-STATE
D9 D8
A1 A0 D9 D8 D7
D8D9A0
A1
A2
D9
t
18
t
19
t
19
t
21
t
20
t
22
t
23
t
24
NOTE
I = INPUT, O = OUTPUT
t
25
Figure 7. Baseband Serial Port BSPORT
t
1
t
2
t
3
Figure 2. Clock Timing
100mAI
OL
TO OUTPUT PIN
+2.1V
100mA
I
OH
C
L
15pF
Figure 3. Load Circuit for Timing Specifications
t
6
t
4
t
1
t
3
t
2
t
5
MCLK
*ASCLK
*ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY
(MCLK/4 SHOWN HERE).
Figure 4. ASCLK
t
9
t
7
t
1
t
3
t
2
t
8
MCLK
*BSCLK
*BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY
(MCLK/4 SHOWN HERE).
Figure 5. BSCLK

AD7729ARU-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 3V Dual w/ Aux DAC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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