© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 15
1 Publication Order Number:
MC100LVEP210/D
MC100LVEP210
2.5V / 3.3V 1:5 Dual
Differential ECL/PECL/HSTL
Clock Driver
Description
The MC100LVEP210 is a low skew 1−to−5 dual differential driver,
designed with clock distribution in mind. The ECL/PECL input
signals can be either differential or single−ended if the V
BB
output is
used. The signal is fanned out to 5 identical differential outputs. HSTL
inputs can be used when the EP210 is operating in PECL mode.
The LVEP210 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure the tight skew specification is realized, both sides of the
differential output need to be terminated identically into 50 W even if
only one output is being used. If an output pair is unused, both outputs
may be left open (unterminated) without affecting skew.
The MC100LVEP210, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This allows the
LVEP210 to be used for high performance clock distribution in +3.3 V
or +2.5 V systems. Single−ended CLK input operation is limited to a
V
CC
≥ 3.0 V in PECL mode, or V
EE
≤ −3.0 V in ECL mode.
Designers can take advantage of the LVEP210’s performance to
distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For more
information on using PECL, designers should refer to Application
Note AN1406/D.
Features
• 85 ps Typical Device−to−Device Skew
• 20 ps Typical Output−to−Output Skew
• V
BB
Output
• Jitter Less than 1 ps RMS
• 350 ps Typical Propagation Delay
• Maximum Frequency u 3 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode Operating Range: V
CC
= 2.375 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −2.375 V to −3.8 V
• Open Input Default State
• LVDS Input Compatible
• Fully Compatible with MC100EP210
• These are Pb−Free Devices
32−LEAD LQFP
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
MC100
LVEP21
AWLYYWWG
32
1
MC100
LVEP210
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
(Note: Microdot may be in either location)
