LTC3722-1/LTC3722-2
7
372212fb
For more information www.linear.com/LTC3722
PIN FUNCTIONS
SYNC (Pin 1/Pin 1): Synchronization Input/Output for the
Oscillator. The input threshold for SYNC is approximately
1.9V, making it compatible with both CMOS and TTL logic.
Terminate SYNC with a 5.1k resistor to GND.
DPRG (Pin 2/Pin 5): Programming Input for Default Zero
Voltage Transition (ZVS) Delay. Connect a resistor from
DPRG to V
REF
to set the maximum turn on delay for outputs
A, B, C, D. The nominal voltage on DPRG is 2V.
RAMP (NA/Pin 2): Input to Phase Modulator Comparator
for LTC3722-2 only. The voltage on RAMP is internally
level shifted by 650mV.
CS (Pin 3/Pin 3): Input to Phase Modulator for the
LTC3722-1. Input to pulse-by-pulse and overload current
limit comparators, output of slope compensation circuitry.
The pulse by pulse comparator has a nominal 300mV
threshold, while the overload comparator has a nominal
650mV threshold.
COMP (Pin 4/Pin 4): Error Amplifier Output, Inverting
Input to Phase Modulator.
R
LEB
(Pin 5/NA): Timing Resistor for Leading Edge Blank-
ing. Use a 10k to 100k resistor to program from 40ns to
310ns of leading edge blanking of the current sense signal
on CS for the LTC3722-1. A ±1% tolerance resistor is
recommended. The LTC3722-2 has a fixed blanking time
of approximately 80ns.
FB (Pin 6/Pin 6): Error Amplifier Inverting Input. This is
the voltage feedback input for the LTC3722. The nominal
regulation voltage at FB is 1.204V.
SS (Pin 7/Pin 7): Soft-Start/Restart Delay Circuitry Timing
Capacitor. A capacitor from SS to GND provides a controlled
ramp of the current command (LTC3722-1), or duty cycle
(LTC3722-2). During overload conditions SS is discharged
to ground initiating a soft-start cycle.
NC (Pin 8/Pin 8): No Connection. Tie this pin to GND.
PDLY (Pin 9/Pin 9): Passive Leg Delay Circuit Input. PDLY
is connected through a voltage divider to the left leg of
the bridge in adaptive ZVS mode. In fixed ZVS mode, a
voltage between 0V and 2.5V on PDLY, programs a fixed
ZVS delay time for the passive leg transition.
SBUS (Pin 10/Pin 10): Line Voltage Sense Input. SBUS is
connected to the main DC voltage feed by a resistive volt-
age divider when using adaptive ZVS control. The voltage
divider is designed to produce 1.5V on SBUS at nominal
V
IN
. If SBUS is tied to V
REF
, the LTC3722-1/LTC3722-2 is
configured for fixed mode ZVS control.
ADLY (Pin 11/Pin 11): Active Leg Delay Circuit Input. ADLY
is connected through a voltage divider to the right leg of
the bridge in adaptive ZVS mode. In fixed ZVS mode, a
voltage between 0V and 2.5V on ADLY, programs a fixed
ZVS delay time for the active leg transition.
UVLO (Pin 12/Pin 12): Input to Program System Turn-
On and Turn-Off Voltages. The nominal threshold of the
UVLO comparator is 5V. UVLO is connected to the main
DC system feed through a resistor divider. When the
UVLO threshold is exceeded, the LTC3722-1/LTC3722-2
commences a soft-start cycle and a 10µA (nominal) cur-
rent is fed out of UVLO to program the desired amount of
system hysteresis. The hysteresis level can be adjusted
by changing the resistance of the divider.
SPRG (Pin 13/Pin 13): A resistor is connected between
SPRG and GND to set the turn-off delay for the synchronous
rectifier driver outputs (OUTE and OUTF). The nominal
voltage on SPRG is 2V.
V
REF
(Pin 14/Pin 14): Output of the 5V Reference. V
REF
is capable of supplying up to 18mA to external circuitry.
V
REF
should be decoupled to GND with a 1µF ceramic
capacitor.
OUTF (Pin 15/Pin 15): 50mA Driver for Synchronous
Rectifier Associated with OUTB and OUTC.
OUTE (Pin 16/Pin 16): 50mA Driver for Synchronous
Rectifier Associated with OUTA and OUTD.
OUTD (Pin 17/Pin 17): 50mA Driver for Low Side of the
Full Bridge Active Leg.
V
CC
(Pin 18/Pin 18): Supply Voltage Input to the
LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator.
The chip is enabled after V
CC
has risen high enough to
allow the V
CC
shunt regulator to conduct current and the
UVLO comparator threshold is exceeded. Once the V
CC
shunt regulator has turned on, V
CC
can drop to as low as
6V (typ) and maintain operation.
(LTC3722-1/LTC3722-2)
LTC3722-1/LTC3722-2
8
372212fb
For more information www.linear.com/LTC3722
BLOCK DIAGRAM
PIN FUNCTIONS
(LTC3722-1/LTC3722-2)
OUTC (Pin 19/Pin 19): 50mA Driver for High Side of the
Full Bridge Active Leg.
OUTB (Pin 20/Pin 20): 50mA Driver for Low Side of the
Full Bridge Passive Leg.
OUTA (Pin 21/Pin 21): 50mA Driver for High Side of the
Full Bridge Passive Leg.
PGND (Pin 22/Pin 22): Power Ground for the LTC3722.
The output drivers of the LTC3722 are referenced to
PGND. Connect the ceramic V
CC
bypass capacitor di-
rectly to PGND.
GND (Pin 23/Pin 23): All circuits other than the output
drivers in the LTC3722 are referenced to GND. Use of a
ground plane is recommended but not absolutely neces-
sary.
C
T
(Pin 24/Pin 24): Timing Capacitor for the Oscillator.
Use a ±5% or better low ESR ceramic capacitor for best
results.
LTC3722-1 Current Mode SYNC Phase-Shift PWM
OUTE
OUTF
OUTC
OUTD
ADLY
PGND
PDLY
OUTA
OUTB
372212 BD01
+
+
+
+
+
3
7
6
18 12 14
17
11
22
19
15
16
20
9
21
24
23
1 13 102
4
5
V
CC
UVLO
10.25V = ON
6V = OFF
5V
REF AND LDO
1.2V
REF GOOD
FAULT
LOGIC
SHUTDOWN
CURRENT
LIMIT
PULSE BY PULSE
CURRENT LIMIT
650mV
SLOPE
COMPENSATION
C
T
/R
BLANK
SS
CS
R
LEB
QB
Q
R
S
QB
R
S
R2
14.9k
M1
20Ω
V
REF
1.2V
5V
+
650mV
R1
50k
PHASE
MODULATOR
ERROR
AMPLIFIER
FB
COMP
12µA
300mV
V
CC
GOOD
1 = ENABLE
0 = DISABLE
OSC
ACTIVE
DELAY
SYNC
RECTIFIER
DRIVE
LOGIC
PASSIVE
DELAY
QB
Q
T
V
CC
UVLO V
REF
C
T
SYNC SPRG SBUSDPRG
GND
SYSTEM
UVLO
M2
LTC3722-1/LTC3722-2
9
372212fb
For more information www.linear.com/LTC3722
BLOCK DIAGRAM
LTC3722-2 Voltage Mode SYNC Phase-Shift PWM
OUTE
OUTF
OUTC
OUTD
ADLY
PGND
PDLY
OUTA
OUTB
372212 BD02
+
+
+
+
+
3
7
6
18 12 14
17
11
22
19
15
16
20
9
21
24
23
1 13 105
4
V
CC
UVLO
10.25V = ON
6V = OFF
5V
REF AND LDO
1.2V
REF GOOD
FAULT
LOGIC
SHUTDOWN
CURRENT
LIMIT
PULSE BY PULSE
CURRENT LIMIT
650mV
BLANK
SS
2
RAMP
CS
QB
Q
R
S
QB
R
S
V
REF
1.2V
5V
+
650mV
R1
50k
PHASE
MODULATOR
ERROR
AMPLIFIER
FB
COMP
12µA
300mV
V
CC
GOOD
1 = ENABLE
0 = DISABLE
OSC
ACTIVE
DELAY
SYNC
RECTIFIER
DRIVE
LOGIC
PASSIVE
DELAY
QB
Q
T
V
CC
UVLO V
REF
C
T
SYNC SPRG SBUSDPRG
GND
SYSTEM
UVLO
M2

LTC3722IGN-2#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Sync 2x Mode PhModulated Full Bridge Cnt
Lifecycle:
New from this manufacturer.
Delivery:
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